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Date: Wed, 6 Jun 2012 07:37:43 -0700
From: Andi Kleen <ak@...ux.intel.com>
To: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc: Andi Kleen <andi@...stfloor.org>, linux-kernel@...r.kernel.org,
eranian@...gle.com
Subject: Re: [PATCH 3/5] perf, x86: Check LBR format capability
On Wed, Jun 06, 2012 at 04:22:36PM +0200, Peter Zijlstra wrote:
> On Wed, 2012-06-06 at 07:14 -0700, Andi Kleen wrote:
> > On Wed, Jun 06, 2012 at 12:40:24PM +0200, Peter Zijlstra wrote:
> > > On Tue, 2012-06-05 at 17:56 -0700, Andi Kleen wrote:
> > > > From: Andi Kleen <ak@...ux.intel.com>
> > > >
> > > > Double check the CPU has a LBR format we support before using it.
> > > >
> > > > Also I made the init functions __init while I was on it.
> > >
> > > Why? Its all after a model test anyway.
> >
> > Because the spec says we should check it.
>
> The spec says lots of things.. but being that LBR is very much model
> specific I really can't be bothered.
Well you don't need to be, I did it already :-)
>
> > It could catch bad VMs and other inconsistencies and it's the right thing
> > to do.
>
> That might be a reason, but does it?, and why wasn't that in the
> changelog?
No it will not catch KVM because zero is a valid version :-/
That would still need the MISC_ENABLE re-read I think.
Still it's the right thing to do I believe.
-andi
--
ak@...ux.intel.com -- Speaking for myself only
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