linux-kernel - Re: [PATCH 1/2] perf, x86: Add basic Ivy Bridge support

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Message-ID: <CABPqkBSEknXdTQWCrxeeeFgREX02ARRzxJ8bj6uh+0yOi0nAjg@mail.gmail.com>
Date:	Fri, 8 Jun 2012 00:37:39 +0200
From:	Stephane Eranian <eranian@...gle.com>
To:	Andi Kleen <andi@...stfloor.org>
Cc:	linux-kernel@...r.kernel.org, peterz@...radead.org, mingo@...e.hu,
	Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH 1/2] perf, x86: Add basic Ivy Bridge support

On Fri, Jun 8, 2012 at 12:29 AM, Andi Kleen <andi@...stfloor.org> wrote:
> From: Andi Kleen <ak@...ux.intel.com>
>
> Very similar to Sandy Bridge, but there is no PEBS problem.
>
> Signed-off-by: Andi Kleen <ak@...ux.intel.com>
> ---
>  arch/x86/kernel/cpu/perf_event_intel.c |    9 ++++++++-
>  1 files changed, 8 insertions(+), 1 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index 166546e..1249c56 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -1698,6 +1698,7 @@ __init int intel_pmu_init(void)
>        union cpuid10_ebx ebx;
>        unsigned int unused;
>        int version;
> +       char *name;
>
>        if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
>                switch (boot_cpu_data.x86) {
> @@ -1839,9 +1840,15 @@ __init int intel_pmu_init(void)
>                pr_cont("Westmere events, ");
>                break;
>
> +       case 58: /* IvyBridge */
> +               name = "Ivy";
> +               goto snb_ivb_common;
> +
>        case 42: /* SandyBridge */
>                x86_add_quirk(intel_sandybridge_quirk);
>        case 45: /* SandyBridge, "Romely-EP" */
> +               name = "Sandy";
> +       snb_ivb_common:
>                memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
>                       sizeof(hw_cache_event_ids));
>
> @@ -1861,7 +1868,7 @@ __init int intel_pmu_init(void)
>                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
>                        X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
>

But as far as I know for the other generic stall event:
               /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
                        X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);

Event 0xb1, umask 0x1 does not exist on IVB. Only the
UOPS_DISPATCHED.CORE version does.
Given I don't have a definition for STALLED_CYCLES_BACKEND, I don't
know if measuring across
both HT thread would fit the bill. I would advise you keep this one
undefined on IVB otherwise this
may lead to confusion when comparing with SNB.


> -               pr_cont("SandyBridge events, ");
> +               pr_cont("%sBridge events, ", name);
>                break;
>
>        default:
> --
> 1.7.7.6
>
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