linux-kernel - Re: [RFC 23/23] ARM: keystone: add switch over to high physical address range

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Date:	Tue, 24 Jul 2012 14:39:25 +0000
From:	Arnd Bergmann <arnd@...db.de>
To:	Cyril Chemparathy <cyril@...com>
Cc:	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	nico@...aro.org, will.deacon@....com, catalin.marinas@....com,
	Vitaly Andrianov <vitalya@...com>
Subject: Re: [RFC 23/23] ARM: keystone: add switch over to high physical address range

On Tuesday 24 July 2012, Cyril Chemparathy wrote:
> Keystone platforms have their physical memory mapped at an address outside the
> 32-bit physical range.  A Keystone machine with 16G of RAM would find its
> memory at 0x0800000000 - 0x0bffffffff.
> 
> For boot purposes, the interconnect supports a limited alias of some of this
> memory within the 32-bit addressable space (0x80000000 - 0xffffffff).  This
> aliasing is implemented in hardware, and is not intended to be used much
> beyond boot.  For instance, DMA coherence does not work when running out of
> this aliased address space.
> 
> Therefore, we've taken the approach of booting out of the low physical address
> range, and subsequently we switch over to the high range once we're safely
> inside machine specific territory.  This patch implements this switch over
> mechanism, which involves rewiring the TTBRs and page tables to point to the
> new physical address space.
> 
> Signed-off-by: Vitaly Andrianov <vitalya@...com>
> Signed-off-by: Cyril Chemparathy <cyril@...com>

I think this needs some more explanations. Why is not not possible
to use this the larger area from the start when we first enable
paging?
Also, the code does not really look platform specific, so I could
imagine that if you need it, other similar platforms will need the
same thing, and it should be put into common code and enabled
all the time when using LPAE.

	Arnd
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