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Message-ID: <50100CC4.8010706@redhat.com>
Date:	Wed, 25 Jul 2012 11:12:04 -0400
From:	Don Dutile <ddutile@...hat.com>
To:	Jiang Liu <liuj97@...il.com>
CC:	Bjorn Helgaas <bhelgaas@...gle.com>,
	Yijing Wang <wangyijing@...wei.com>,
	Yinghai Lu <yinghai@...nel.org>,
	Taku Izumi <izumi.taku@...fujitsu.com>,
	"Rafael J . Wysocki" <rjw@...k.pl>,
	Kenji Kaneshige <kaneshige.kenji@...fujitsu.com>,
	linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org
Subject: Re: [RFC PATCH v2 01/32] PCI: add pcie_flags_reg into struct pci_dev
 to cache PCIe capabilities register

resending since i did a reply vs reply-all last time...

On 07/24/2012 12:31 PM, Jiang Liu wrote:
> From: Yijing Wang<wangyijing@...wei.com>
>
> From: Yijing Wang<wangyijing@...wei.com>
>
> Since PCI Express Capabilities Register is read only, cache its value
> into struct pci_dev to avoid repeatedly calling pci_read_config_*().
>
> Signed-off-by: Yijing Wang<wangyijing@...wei.com>
> Signed-off-by: Jiang Liu<liuj97@...il.com>
> ---
>   drivers/pci/probe.c |    1 +
>   include/linux/pci.h |   10 ++++++++++
>   2 files changed, 11 insertions(+)
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 6c143b4..6fd58df 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -929,6 +929,7 @@ void set_pcie_port_type(struct pci_dev *pdev)
>   	pdev->is_pcie = 1;
>   	pdev->pcie_cap = pos;
>   	pci_read_config_word(pdev, pos + PCI_EXP_FLAGS,&reg16);
> +	pdev->pcie_flags_reg = reg16;
>   	pdev->pcie_type = (reg16&  PCI_EXP_FLAGS_TYPE)>>  4;
So, given the patch below, shouldn't the above line be ?
     pdev->pcie_type = pci_pcie_type(pdev);

Missed part of patch ?

>   	pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP,&reg16);
>   	pdev->pcie_mpss = reg16&  PCI_EXP_DEVCAP_PAYLOAD;
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 5faa831..95662b2 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -258,6 +258,7 @@ struct pci_dev {
>   	u8		pcie_mpss:3;	/* PCI-E Max Payload Size Supported */
>   	u8		rom_base_reg;	/* which config register controls the ROM */
>   	u8		pin;  		/* which interrupt pin this device uses */
> +	u16		pcie_flags_reg;	/* cached PCI-E Capabilities Register */
>
>   	struct pci_driver *driver;	/* which driver has allocated this device */
>   	u64		dma_mask;	/* Mask of the bits of bus address this
> @@ -1650,6 +1651,15 @@ static inline bool pci_is_pcie(struct pci_dev *dev)
>   	return !!pci_pcie_cap(dev);
>   }
>
> +/**
> + * pci_pcie_type - get the PCIe device/port type
> + * @dev: PCI device
> + */
> +static inline int pci_pcie_type(const struct pci_dev *dev)
> +{
> +	return (dev->pcie_flags_reg&  PCI_EXP_FLAGS_TYPE)>>  4;
> +}
> +
>   void pci_request_acs(void);
>   bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
>   bool pci_acs_path_enabled(struct pci_dev *start,

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