linux-kernel - Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value for SRC/DST_TR

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Message-ID: <CAKohpo=bvzm1O4FAtsr3YpLg-w1Rp7RT-9ZuJBgVZRxVHnQO_g@mail.gmail.com>
Date:	Mon, 3 Sep 2012 14:00:11 +0530
From:	Viresh Kumar <viresh.kumar@...aro.org>
To:	Andy Shevchenko <andy.shevchenko@...il.com>
Cc:	Hein Tibosch <hein_tibosch@...oo.es>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Hans-Christian Egtvedt <egtvedt@...fundet.no>,
	Arnd Bergmann <arnd.bergmann@...aro.org>,
	spear-devel <spear-devel@...t.st.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	"ludovic.desroches" <ludovic.desroches@...el.com>,
	Havard Skinnemoen <havard@...nnemoen.net>,
	Nicolas Ferre <nicolas.ferre@...el.com>
Subject: Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value for
 SRC/DST_TR_WID register

On 3 September 2012 13:55, Andy Shevchenko <andy.shevchenko@...il.com> wrote:
>> #define DW_MEM_WIDTH_64         0       /* default */
>> #define DW_MEM_WIDTH_32         1       /* e.g. for avr32 */
> There are 4 options: 32, 64, 128, and 256 bits. I would prefer to see
> the value in conjunction with
> real value in the register, namely 2 for 32, 3 - 64, 4 - 128, 5 - 256.

Which register are you talking about? This configuration is outside of DMAC
controller and i am not sure if dw DMAC controller can do 128 or 256
bit transfers.

>> @@ -58,6 +58,9 @@ struct dw_dma_slave {
>>         u32                     cfg_lo;
>>         u8                      src_master;
>>         u8                      dst_master;
>> +#define        DW_MEM_WIDTH_64         0
>> +#define        DW_MEM_WIDTH_32         1       /* e.g. for avr32 */
>> +       u8                      max_mem_width;
> Might be I missed something, but why is it slave configuration?
> I think the controller (actually channel) structure is more suitable
> to keep that field inside.

@Hein: Even i missed it. How will you do memcpy transfers as we don't have
this structure there. Probably you need to move this to DMA controller platform
data filed.

viresh
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