linux-kernel - Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value for SRC/DST_TR

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Date:	Mon, 3 Sep 2012 14:29:03 +0530
From:	Viresh Kumar <viresh.kumar@...aro.org>
To:	Andy Shevchenko <andy.shevchenko@...il.com>
Cc:	Hein Tibosch <hein_tibosch@...oo.es>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Hans-Christian Egtvedt <egtvedt@...fundet.no>,
	Arnd Bergmann <arnd.bergmann@...aro.org>,
	spear-devel <spear-devel@...t.st.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	"ludovic.desroches" <ludovic.desroches@...el.com>,
	Havard Skinnemoen <havard@...nnemoen.net>,
	Nicolas Ferre <nicolas.ferre@...el.com>
Subject: Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value for
 SRC/DST_TR_WID register

On 3 September 2012 14:19, Andy Shevchenko <andy.shevchenko@...il.com> wrote:
> On Mon, Sep 3, 2012 at 11:30 AM, Viresh Kumar <viresh.kumar@...aro.org> wrote:
>> Which register are you talking about? This configuration is outside of DMAC
>> controller and i am not sure if dw DMAC controller can do 128 or 256
>> bit transfers.
> SRC_WIDTH & DST_WIDTH in CTLx. The field are 3 bit long. Acceptable
> values from 0 to 5.
> 2 corresponds to 32 bit transfers.

The field is 3 bit long but only allowable values are 0,1,2 & 3... This is what
i can check in my copy of dw_dmac manual.

4 and 5 aren't valid values.
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