linux-kernel - Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support

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Message-ID: <CABPqkBS1Crg7yHbzrvF7S2YUjrPZNSYRpE7tuax+OcEu4xrHMA@mail.gmail.com>
Date:	Fri, 28 Sep 2012 10:54:45 +0200
From:	Stephane Eranian <eranian@...gle.com>
To:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc:	Andi Kleen <andi@...stfloor.org>,
	LKML <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>,
	Arnaldo Carvalho de Melo <acme@...hat.com>,
	Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH 01/31] perf, x86: Add PEBSv2 record support

On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra <a.p.zijlstra@...llo.nl> wrote:
> On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
>> +               if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
>
> Shouldn't that be: && x86_pmu.intel_cap.pebs_trap, like most other sites
> instead? Or didn't they flip the trap capability on Haswell?

On Haswell, you get the event_ip which points to the sampled
instruction, i.e., the off-by-one
error can be avoided by using that value instead of pebs.rip. The nice
side effect is that you
free the LBR and minimize the overhead (no fixups). Therfore the LBR
filter can have any
setting when combined with PEBS, thus we do not need to check for
compatibility nor force
any setting for the LBR filter.
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