linux-kernel - RE: [PATCH 01/13] calk: davinci

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Message-ID: <3E54258959B69E4282D79E01AB1F32B7041FDA05@DFLE12.ent.ti.com>
Date:	Thu, 11 Oct 2012 14:07:24 +0000
From:	"Karicheri, Muralidharan" <m-karicheri2@...com>
To:	"Nori, Sekhar" <nsekhar@...com>
CC:	"mturquette@...aro.org" <mturquette@...aro.org>,
	"arnd@...db.de" <arnd@...db.de>,
	"akpm@...ux-foundation.org" <akpm@...ux-foundation.org>,
	"shawn.guo@...aro.org" <shawn.guo@...aro.org>,
	"rob.herring@...xeda.com" <rob.herring@...xeda.com>,
	"linus.walleij@...aro.org" <linus.walleij@...aro.org>,
	"viresh.linux@...il.com" <viresh.linux@...il.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"Hilman, Kevin" <khilman@...com>,
	"linux@....linux.org.uk" <linux@....linux.org.uk>,
	"davinci-linux-open-source@...ux.davincidsp.com" 
	<davinci-linux-open-source@...ux.davincidsp.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-keystone@...t.ti.com - Linux developers for Keystone family of
	devices (May contain non-TIers)" <linux-keystone@...t.ti.com>,
	"linux-c6x-dev@...ux-c6x.org" <linux-c6x-dev@...ux-c6x.org>,
	"Chemparathy, Cyril" <cyril@...com>
Subject: RE: [PATCH 01/13] calk: davinci - add Main PLL clock driver

>> -----Original Message-----
>> From: Nori, Sekhar
>> Sent: Thursday, October 11, 2012 6:16 AM
>> To: Karicheri, Muralidharan
>> Cc: mturquette@...aro.org; arnd@...db.de; akpm@...ux-foundation.org;
>> shawn.guo@...aro.org; rob.herring@...xeda.com; linus.walleij@...aro.org;
>> viresh.linux@...il.com; linux-kernel@...r.kernel.org; Hilman, Kevin;
>> linux@....linux.org.uk; davinci-linux-open-source@...ux.davincidsp.com; linux-arm-
>> kernel@...ts.infradead.org; linux-keystone@...t.ti.com - Linux developers for Keystone
>> family of devices (May contain non-TIers); linux-c6x-dev@...ux-c6x.org; Chemparathy,
>> Cyril
>> Subject: Re: [PATCH 01/13] calk: davinci - add Main PLL clock driver
>> 
>> On 10/10/2012 8:04 PM, Karicheri, Muralidharan wrote:
>> 
>> >>>> +struct clk *clk_register_davinci_pll(struct device *dev, const char *name,
>> >>>> +			const char *parent_name,
>> >>>> +			struct clk_davinci_pll_data *pll_data) {
>> >>>> +	struct clk_init_data init;
>> >>>> +	struct clk_davinci_pll *pll;
>> >>>> +	struct clk *clk;
>> >>>> +
>> >>>> +	if (!pll_data)
>> >>>> +		return ERR_PTR(-ENODEV);
>> >>>> +
>> >>>> +	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
>> >>>> +	if (!pll)
>> >>>> +		return ERR_PTR(-ENOMEM);
>> >>>> +	init.name = name;
>> >>>> +	init.ops = &clk_pll_ops;
>> >>>> +	init.flags = pll_data->flags;
>> >>>> +	init.parent_names = (parent_name ? &parent_name : NULL);
>> >>>> +	init.num_parents = (parent_name ? 1 : 0);
>> >>>> +
>> >>>> +	pll->pll_data	= pll_data;
>> >>>> +	pll->hw.init = &init;
>> >>>> +
>> >>>> +	clk = clk_register(NULL, &pll->hw);
>> >>>> +	if (IS_ERR(clk))
>> >>>> +		kfree(pll);
>> >>>> +
>> >>>> +	return clk;
>> >>>> +}
>> >>>
>> >>> I guess there is an an "unregister" required as well which will free
>> >>> the pll memory allocated above and unregister the clock? Not sure if
>> >>> you would ever unregister a PLL, but providing this will probably help symmetry.
>> > Sekhar,
>> >
>> > clk_unregister() itself is a null statement in clk.c. Besides none of the clk drivers
>> presently have implemented the unregister(). So I believe this is unnecessary.
>> 
>> I am ok with this.
>> 
>> > BTW, please review the v2 patch for the rest of the series. For the one you have
>> already reviewed, it should be fine.
>> 
>> Okay. I see those now. BTW, this series also has a v2 in its 0/13. Are there any
>> differences between this and the other v2, or is that merely a resend?
>> 

You are right. I did a re-send to add v2 in all of the patch subject. We are fine.

>> Thanks,
>> Sekhar