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Message-ID: <3E54258959B69E4282D79E01AB1F32B7041FDA2E@DFLE12.ent.ti.com>
Date:	Thu, 11 Oct 2012 14:10:16 +0000
From:	"Karicheri, Muralidharan" <m-karicheri2@...com>
To:	"Nori, Sekhar" <nsekhar@...com>
CC:	"Hilman, Kevin" <khilman@...com>,
	"davinci-linux-open-source@...ux.davincidsp.com" 
	<davinci-linux-open-source@...ux.davincidsp.com>,
	"mturquette@...aro.org" <mturquette@...aro.org>,
	"linux-c6x-dev@...ux-c6x.org" <linux-c6x-dev@...ux-c6x.org>,
	"arnd@...db.de" <arnd@...db.de>,
	"linus.walleij@...aro.org" <linus.walleij@...aro.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"rob.herring@...xeda.com" <rob.herring@...xeda.com>,
	"linux-keystone@...t.ti.com - Linux developers for Keystone family of
	devices (May contain non-TIers)" <linux-keystone@...t.ti.com>,
	"viresh.linux@...il.com" <viresh.linux@...il.com>,
	"linux@....linux.org.uk" <linux@....linux.org.uk>,
	"akpm@...ux-foundation.org" <akpm@...ux-foundation.org>,
	"shawn.guo@...aro.org" <shawn.guo@...aro.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: RE: [PATCH 01/13] clk: davinci - add Main PLL clock driver

>> -----Original Message-----
>> From: Nori, Sekhar
>> Sent: Thursday, October 11, 2012 6:35 AM
>> To: Nori, Sekhar
>> Cc: Karicheri, Muralidharan; Hilman, Kevin; davinci-linux-open-
>> source@...ux.davincidsp.com; mturquette@...aro.org; linux-c6x-dev@...ux-c6x.org;
>> arnd@...db.de; linus.walleij@...aro.org; linux-kernel@...r.kernel.org;
>> rob.herring@...xeda.com; linux-keystone@...t.ti.com - Linux developers for Keystone
>> family of devices (May contain non-TIers); viresh.linux@...il.com;
>> linux@....linux.org.uk; akpm@...ux-foundation.org; shawn.guo@...aro.org; linux-arm-
>> kernel@...ts.infradead.org
>> Subject: Re: [PATCH 01/13] clk: davinci - add Main PLL clock driver
>> 
>> On 10/10/2012 5:32 PM, Sekhar Nori wrote:
>> > Hi Murali,
>> >
>> > On 9/26/2012 11:37 PM, Murali Karicheri wrote:
>> >> This is the driver for the main PLL clock hardware found on DM SoCs.
>> >> This driver borrowed code from arch/arm/mach-davinci/clock.c and
>> >> implemented the driver as per common clock provider API. The main PLL
>> >> hardware typically has a multiplier, a pre-divider and a post-divider.
>> >> Some of the SoCs has the divider fixed meaning they can not be
>> >> configured through a register. HAS_PREDIV and HAS_POSTDIV flags are
>> >> used to tell the driver if a hardware has these dividers present or not.
>> >> Driver is configured through the structure clk_davinci_pll_data that
>> >> has the platform data for the driver.
>> >>
>> >> Signed-off-by: Murali Karicheri <m-karicheri2@...com>
>> >
>> > Are you using git-format-patch to generate the patches? It should have
>> > added a diffstat here by default which is very useful in quickly
>> > understanding what the patch is touching.
>> >>
>> >> diff --git a/drivers/clk/davinci/clk-davinci-pll.c
>> >> b/drivers/clk/davinci/clk-davinci-pll.c
>> 
>> Looking at how common clock framework for mxs has been implemented, this file should
>> simply be clk-pll.c. That makes sense as you are creating a davinci folder anyway. Similar
>> change required for psc as well.
>> 

Alternately, do we need  a davinci folder? Can't we just add it to the clk/ directory? These IPs are re-used in c6x and keystone architectures. So it make sense to keep in the clk folder. If agree, I can make this change in v3.

>> Thanks,
>> Sekhar

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