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Message-ID: <1351524186.24721.29.camel@twins>
Date: Mon, 29 Oct 2012 16:23:06 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Stephane Eranian <eranian@...gle.com>
Cc: linux-kernel@...r.kernel.org, mingo@...e.hu, ak@...ux.intel.com,
acme@...hat.com, jolsa@...hat.com, ming.m.lin@...el.com
Subject: Re: [Patch v1 04/10] perf/x86: add memory profiling via PEBS Load
Latency
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
> +EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x100b,umask=0x1,ldlat=3");
> +EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
I haven't fully grokked the macro magic yet, but event=0x100b seems
wrong, event only takes 8 bit on Intel.
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