linux-kernel - Re: [PATCH 2/2] New driver: Xillybus generic interface for FPGA (programmable logic)

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Date:	Wed, 5 Dec 2012 13:34:59 +0100
From:	Pavel Machek <pavel@....cz>
To:	Philip Balister <philip@...ister.org>
Cc:	Arnd Bergmann <arnd@...db.de>,
	Greg KH <gregkh@...uxfoundation.org>,
	Eli Billauer <eli.billauer@...il.com>,
	linux-kernel@...r.kernel.org, John Linn <john.linn@...inx.com>,
	Michal Simek <michal.simek@...inx.com>,
	"Ira W. Snyder" <iws@...o.caltech.edu>,
	Josh Cartwright <josh.cartwright@...com>, dinguyen@...era.com
Subject: Re: [PATCH 2/2] New driver: Xillybus generic interface for FPGA
 (programmable logic)

Hi!

> >Agreed. If I understand you correctly though, your approach is specific
> >to a particular hardware implementation (Zynq) on the user interface layer,
> >which I think is exactly what we should avoid. Obviously, there is
> >always a driver involved that is specific to the IP block you load into
> >an FPGA at runtime, and that is ok. The two parts that I think we
> >should agree on are:

> The approach I am taking is not Zynq specific. The only Zynq
> specific bits will be range checking data from the device tree to
> make sure the user is mapping address space that is used by the FPGA
> and a similar validation of the IRQ numbers. I have not looked at
> the Altera part closely, but I suspect their fpga/processor
> interface may use similar concepts.

So... the arch may be called socfpga, but I don't think we managed to
merge actual fpga parts, yet ;-). In fact, I'm not sure if I actually
seen those... Dinh should know more about status there.
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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