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Date:	Fri, 25 Jan 2013 12:06:25 +0100
From:	Linus Walleij <linus.walleij@...aro.org>
To:	Paul Bolle <pebolle@...cali.nl>
Cc:	Aaron Sierra <asierra@...-inc.com>,
	Peter Hurley <peter@...leysoftware.com>,
	Samuel Ortiz <sameo@...ux.intel.com>,
	Agócs Pál <agocs.pal.86@...il.com>,
	LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3] lpc_ich: fix gpio base and control offsets

On Fri, Jan 25, 2013 at 11:04 AM, Paul Bolle <pebolle@...cali.nl> wrote:
> On Fri, 2013-01-25 at 10:47 +0100, Linus Walleij wrote:
>> On Thu, Jan 24, 2013 at 9:52 PM, Aaron Sierra <asierra@...-inc.com> wrote:
>> > In ICH5 and earlier the GPIOBASE and GPIOCTRL registers are found at
>> > offsets 0x58 and 0x5C, respectively. This patch allows GPIO access to
>> > properly be enabled (and disabled) for these chipsets.
>> >
>> > Signed-off-by: Agócs Pál <agocs.pal.86@...il.com>
>> > Signed-off-by: Aaron Sierra <asierra@...-inc.com>
>>
>> OK... Paul, can you test this on your setup?
>
> This seems to be the first time I'm added to this thread. I'm a bit lost
> here: why should I test this patch? This doesn't seem to be related to
> two older lpc_ich threads I was involved in (in November 2012). Not that
> I mind testing stuff, that's not the problem...

Basically I do git log and when I see this I think:

commit 0c418844dce21fa7000b51190f393c7d6a7ee12d
Author: Paul Bolle <pebolle@...cali.nl>
Date:   Mon Nov 19 21:04:11 2012 +0100

    mfd: lpc_ich: One uninitialized cell is no error

"Hm, there is another guy who's actually using this hardware."

"If this patch breaks it he will probably be upset."

Yours,
Linus Walleij
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