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Message-ID: <1359108275.6647.4.camel@x61.thuisdomein>
Date:	Fri, 25 Jan 2013 11:04:35 +0100
From:	Paul Bolle <pebolle@...cali.nl>
To:	Linus Walleij <linus.walleij@...aro.org>
Cc:	Aaron Sierra <asierra@...-inc.com>,
	Peter Hurley <peter@...leysoftware.com>,
	Samuel Ortiz <sameo@...ux.intel.com>,
	Agócs Pál <agocs.pal.86@...il.com>,
	LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3] lpc_ich: fix gpio base and control offsets

On Fri, 2013-01-25 at 10:47 +0100, Linus Walleij wrote:
> On Thu, Jan 24, 2013 at 9:52 PM, Aaron Sierra <asierra@...-inc.com> wrote:
> > In ICH5 and earlier the GPIOBASE and GPIOCTRL registers are found at
> > offsets 0x58 and 0x5C, respectively. This patch allows GPIO access to
> > properly be enabled (and disabled) for these chipsets.
> >
> > Signed-off-by: Agócs Pál <agocs.pal.86@...il.com>
> > Signed-off-by: Aaron Sierra <asierra@...-inc.com>
> 
> OK... Paul, can you test this on your setup?

This seems to be the first time I'm added to this thread. I'm a bit lost
here: why should I test this patch? This doesn't seem to be related to
two older lpc_ich threads I was involved in (in November 2012). Not that
I mind testing stuff, that's not the problem...


Paul Bolle

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