linux-kernel - [tip:x86/cpu] x86, cpu, amd: Fix WC+ workaround for older virtual hosts

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Date:	Tue, 19 Feb 2013 11:29:19 -0800
From:	tip-bot for Borislav Petkov <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...nel.org,
	boris.ostrovsky@...cle.com, gleb@...hat.com, tglx@...utronix.de,
	bp@...e.de, hpa@...ux.intel.com
Subject: [tip:x86/cpu] x86, cpu, amd:
  Fix WC+ workaround for older virtual hosts

Commit-ID:  52d3d06e706bdde3d6c5c386deb065c3b4c51618
Gitweb:     http://git.kernel.org/tip/52d3d06e706bdde3d6c5c386deb065c3b4c51618
Author:     Borislav Petkov <bp@...e.de>
AuthorDate: Tue, 19 Feb 2013 19:33:12 +0100
Committer:  H. Peter Anvin <hpa@...ux.intel.com>
CommitDate: Tue, 19 Feb 2013 10:44:00 -0800

x86, cpu, amd: Fix WC+ workaround for older virtual hosts

The WC+ workaround for F10h introduces a new MSR and kvm host #GPs
on accesses to unknown MSRs if paravirt is not compiled in. Use the
exception-handling MSR accessors so as not to break 3.8 and later guests
booting on older hosts.

Remove a redundant family check while at it.

Cc: Gleb Natapov <gleb@...hat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@...cle.com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Link: http://lkml.kernel.org/r/1361298793-31834-1-git-send-email-bp@alien8.de
Signed-off-by: H. Peter Anvin <hpa@...ux.intel.com>
---
 arch/x86/kernel/cpu/amd.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 721ef32..163af4a 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -723,12 +723,14 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 		 * performance degradation for certain nested-paging guests.
 		 * Prevent this conversion by clearing bit 24 in
 		 * MSR_AMD64_BU_CFG2.
+		 *
+		 * NOTE: we want to use the _safe accessors so as not to #GP kvm
+		 * guests on older kvm hosts.
 		 */
-		if (c->x86 == 0x10) {
-			rdmsrl(MSR_AMD64_BU_CFG2, value);
-			value &= ~(1ULL << 24);
-			wrmsrl(MSR_AMD64_BU_CFG2, value);
-		}
+
+		rdmsrl_safe(MSR_AMD64_BU_CFG2, &value);
+		value &= ~(1ULL << 24);
+		wrmsrl_safe(MSR_AMD64_BU_CFG2, value);
 	}
 
 	rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
--
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