linux-kernel - Re: [PATCH 4/5] perf, x86: Support full width counting v3

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20130222134630.GA8960@gmail.com>
Date:	Fri, 22 Feb 2013 14:46:30 +0100
From:	Ingo Molnar <mingo@...nel.org>
To:	Andi Kleen <andi@...stfloor.org>
Cc:	linux-kernel@...r.kernel.org, Andi Kleen <ak@...ux.intel.com>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Arnaldo Carvalho de Melo <acme@...radead.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Andrew Morton <akpm@...ux-foundation.org>
Subject: Re: [PATCH 4/5] perf, x86: Support full width counting v3


* Andi Kleen <andi@...stfloor.org> wrote:

> From: Andi Kleen <ak@...ux.intel.com>
> 
> Recent Intel CPUs like Haswell and IvyBridge have a new 
> alternative MSR range for perfctrs that allows writing the 
> full counter width. Enable this range if the hardware reports 
> it using a new capability bit.
> 
> This lowers the overhead of perf stat slightly because it has 
> to do less interrupts to accumulate the counter value. On 
> Haswell it also avoids some problems with TSX aborting when 
> the end of the counter range is reached.

The changelog does not adequately explain why this patch is 
critical for basic Haswell enablement. "Avoids some problems 
with TSX aborting" is not very helpful.

Thanks,

	Ingo
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/