linux-kernel - linux-next: manual merge of the l2-mtd tree with the mtd tree

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Message-Id: <20130315115825.6c2b7ad9c48c82640ff9f3b8@canb.auug.org.au>
Date:	Fri, 15 Mar 2013 11:58:25 +1100
From:	Stephen Rothwell <sfr@...b.auug.org.au>
To:	Artem Bityutskiy <dedekind1@...il.com>
Cc:	linux-next@...r.kernel.org, linux-kernel@...r.kernel.org,
	Brian Norris <computersforpeace@...il.com>,
	David Woodhouse <dwmw2@...radead.org>
Subject: linux-next: manual merge of the l2-mtd tree with the mtd tree

Hi Artem,

Today's linux-next merge of the l2-mtd tree got a conflict in
include/linux/mtd/nand.h between commit 5bc7c33ca93a ("mtd: nand:
reintroduce NAND_NO_READRDY as NAND_NEED_READRDY") from the mtd tree and
commit edac3311879c ("mtd: nand: remove AG-AND support") from the l2-mtd
tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    sfr@...b.auug.org.au

diff --cc include/linux/mtd/nand.h
index ef52d9c,33516eb..0000000
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@@ -165,35 -145,8 +145,15 @@@ typedef enum 
   */
  /* Buswidth is 16 bit */
  #define NAND_BUSWIDTH_16	0x00000002
- /* Device supports partial programming without padding */
- #define NAND_NO_PADDING		0x00000004
  /* Chip has cache program function */
  #define NAND_CACHEPRG		0x00000008
- /* Chip has copy back function */
- #define NAND_COPYBACK		0x00000010
- /*
-  * AND Chip which has 4 banks and a confusing page / block
-  * assignment. See Renesas datasheet for further information.
-  */
- #define NAND_IS_AND		0x00000020
- /*
-  * Chip has a array of 4 pages which can be read without
-  * additional ready /busy waits.
-  */
- #define NAND_4PAGE_ARRAY	0x00000040
- /*
-  * Chip requires that BBT is periodically rewritten to prevent
-  * bits from adjacent blocks from 'leaking' in altering data.
-  * This happens with the Renesas AG-AND chips, possibly others.
-  */
- #define BBT_AUTO_REFRESH	0x00000080
 +/*
 + * Chip requires ready check on read (for auto-incremented sequential read).
 + * True only for small page devices; large page devices do not support
 + * autoincrement.
 + */
 +#define NAND_NEED_READRDY	0x00000100
 +
  /* Chip does not allow subpage writes */
  #define NAND_NO_SUBPAGE_WRITE	0x00000200
  

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