| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <1363767266.3758.4.camel@phoenix>
Date: Wed, 20 Mar 2013 16:14:26 +0800
From: Axel Lin <axel.lin@...ics.com>
To: MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>
Cc: linux-kernel@...r.kernel.org
Subject: [PATCH 1/2] PM / devfreq: exynos4_bus: Constify clock divider table
These tables are never modified, make them const.
Signed-off-by: Axel Lin <axel.lin@...ics.com>
---
drivers/devfreq/exynos4_bus.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
index 3f37f3b..45d00d1 100644
--- a/drivers/devfreq/exynos4_bus.c
+++ b/drivers/devfreq/exynos4_bus.c
@@ -177,7 +177,7 @@ static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = {
};
/*** Clock Divider Data for Exynos4210 ***/
-static unsigned int exynos4210_clkdiv_dmc0[][8] = {
+static const unsigned int exynos4210_clkdiv_dmc0[][8] = {
/*
* Clock divider value for following
* { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
@@ -191,7 +191,7 @@ static unsigned int exynos4210_clkdiv_dmc0[][8] = {
/* DMC L2: 133MHz */
{ 5, 1, 1, 5, 1, 1, 3, 1 },
};
-static unsigned int exynos4210_clkdiv_top[][5] = {
+static const unsigned int exynos4210_clkdiv_top[][5] = {
/*
* Clock divider value for following
* { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
@@ -203,7 +203,7 @@ static unsigned int exynos4210_clkdiv_top[][5] = {
/* ACLK200 L2: 133MHz */
{ 5, 7, 7, 7, 1 },
};
-static unsigned int exynos4210_clkdiv_lr_bus[][2] = {
+static const unsigned int exynos4210_clkdiv_lr_bus[][2] = {
/*
* Clock divider value for following
* { DIVGDL/R, DIVGPL/R }
@@ -217,7 +217,7 @@ static unsigned int exynos4210_clkdiv_lr_bus[][2] = {
};
/*** Clock Divider Data for Exynos4212/4412 ***/
-static unsigned int exynos4x12_clkdiv_dmc0[][6] = {
+static const unsigned int exynos4x12_clkdiv_dmc0[][6] = {
/*
* Clock divider value for following
* { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
@@ -235,7 +235,7 @@ static unsigned int exynos4x12_clkdiv_dmc0[][6] = {
/* DMC L4: 100MHz */
{7, 1, 1, 7, 1, 1},
};
-static unsigned int exynos4x12_clkdiv_dmc1[][6] = {
+static const unsigned int exynos4x12_clkdiv_dmc1[][6] = {
/*
* Clock divider value for following
* { G2DACP, DIVC2C, DIVC2C_ACLK }
@@ -252,7 +252,7 @@ static unsigned int exynos4x12_clkdiv_dmc1[][6] = {
/* DMC L4: 100MHz */
{7, 7, 1},
};
-static unsigned int exynos4x12_clkdiv_top[][5] = {
+static const unsigned int exynos4x12_clkdiv_top[][5] = {
/*
* Clock divider value for following
* { DIVACLK266_GPS, DIVACLK100, DIVACLK160,
@@ -270,7 +270,7 @@ static unsigned int exynos4x12_clkdiv_top[][5] = {
/* ACLK_GDL/R L4: 100MHz */
{7, 7, 7, 7, 1},
};
-static unsigned int exynos4x12_clkdiv_lr_bus[][2] = {
+static const unsigned int exynos4x12_clkdiv_lr_bus[][2] = {
/*
* Clock divider value for following
* { DIVGDL/R, DIVGPL/R }
@@ -287,7 +287,7 @@ static unsigned int exynos4x12_clkdiv_lr_bus[][2] = {
/* ACLK_GDL/R L4: 100MHz */
{7, 1},
};
-static unsigned int exynos4x12_clkdiv_sclkip[][3] = {
+static const unsigned int exynos4x12_clkdiv_sclkip[][3] = {
/*
* Clock divider value for following
* { DIVMFC, DIVJPEG, DIVFIMC0~3}
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists