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Message-ID: <1363767334.3758.5.camel@phoenix>
Date:	Wed, 20 Mar 2013 16:15:34 +0800
From:	Axel Lin <axel.lin@...ics.com>
To:	MyungJoo Ham <myungjoo.ham@...sung.com>
Cc:	Kyungmin Park <kyungmin.park@...sung.com>,
	linux-kernel@...r.kernel.org
Subject: [PATCH 2/2] PM / devfreq: exynos4_bus: Fix table entry size for
 exynos4x12_clkdiv_dmc1

exynos4x12_clkdiv_dmc1 contains { G2DACP, DIVC2C, DIVC2C_ACLK }, thus
set the size to 3 rather than 6.

Signed-off-by: Axel Lin <axel.lin@...ics.com>
---
 drivers/devfreq/exynos4_bus.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
index 45d00d1..1deee09 100644
--- a/drivers/devfreq/exynos4_bus.c
+++ b/drivers/devfreq/exynos4_bus.c
@@ -235,7 +235,7 @@ static const unsigned int exynos4x12_clkdiv_dmc0[][6] = {
 	/* DMC L4: 100MHz */
 	{7, 1, 1, 7, 1, 1},
 };
-static const unsigned int exynos4x12_clkdiv_dmc1[][6] = {
+static const unsigned int exynos4x12_clkdiv_dmc1[][3] = {
 	/*
 	 * Clock divider value for following
 	 * { G2DACP, DIVC2C, DIVC2C_ACLK }
-- 
1.7.9.5



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