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Message-ID: <20130423095337.GA26010@localhost.localdomain>
Date: Tue, 23 Apr 2013 17:53:37 +0800
From: Zhao Chenhui <chenhui.zhao@...escale.com>
To: Kumar Gala <galak@...nel.crashing.org>,
Scott Wood <scottwood@...escale.com>
CC: <linux-kernel@...r.kernel.org>, <linuxppc-dev@...ts.ozlabs.org>
Subject: Re: [linuxppc-release] [PATCH v2 01/15] powerpc/85xx: cache
operations for Freescale SoCs based on BOOK3E
Hi Kumar, Scott,
Do you have any comments on this set of patches?
Best Regards,
-Chenhui
On Fri, Apr 19, 2013 at 06:47:34PM +0800, Zhao Chenhui wrote:
> These cache operations support Freescale SoCs based on BOOK3E.
> Move L1 cache operations to fsl_booke_cache.S in order to maintain
> easily. And, add cache operations for backside L2 cache and platform cache.
>
> The backside L2 cache appears on e500mc and e5500 core. The platform cache
> supported by this patch is L2 Look-Aside Cache, which appears on SoCs
> with e500v1/e500v2 core, such as MPC8572, P1020, etc.
>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@...escale.com>
> Signed-off-by: Li Yang <leoli@...escale.com>
> ---
> arch/powerpc/include/asm/cacheflush.h | 8 ++
> arch/powerpc/kernel/Makefile | 1 +
> arch/powerpc/kernel/fsl_booke_cache.S | 210 +++++++++++++++++++++++++++++++++
> arch/powerpc/kernel/head_fsl_booke.S | 74 ------------
> 4 files changed, 219 insertions(+), 74 deletions(-)
> create mode 100644 arch/powerpc/kernel/fsl_booke_cache.S
>
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