linux-kernel - Re: x86/pci/mrst: force all pci config toward 0:0:0, 0:2:0 and 0:3:0 to type 1

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Message-ID: <CAErSpo6g0xXo+HH+ZOYZav_Y6ZUH2D2FAqN+uDqrJqxQCRObog@mail.gmail.com>
Date:	Wed, 1 May 2013 11:17:10 -0600
From:	Bjorn Helgaas <bhelgaas@...gle.com>
To:	Bin Gao <bin.gao@...ux.intel.com>
Cc:	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>,
	"x86@...nel.org" <x86@...nel.org>,
	Jacob Pan <jacob.jun.pan@...ux.intel.com>,
	Jesse Barnes <jbarnes@...tuousgeek.org>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: x86/pci/mrst: force all pci config toward 0:0:0, 0:2:0 and 0:3:0
 to type 1

On Tue, Apr 30, 2013 at 1:21 AM, Bin Gao <bin.gao@...ux.intel.com> wrote:
> x86/pci/mrst: force all pci config access toward 0:0:0, 0:2:0 and 0:3:0 to type 1
>
> For real pci devices 0:0:0, 0:2:0 and 0:3:0, there is either no pci shim, or
> no guarantee of data correctness of offset 256-4k. So for whatever reason,
> Linux kernel should not do MMCFG pci config access to those devices. Instead,
> always use type 1 for those devices.
>
> Signed-off-by: Bin Gao <bin.gao@...ux.intel.com>
> ---
>  arch/x86/pci/mrst.c |   10 ++++++----
>  1 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
> index 6eb18c4..0e0fabf 100644
> --- a/arch/x86/pci/mrst.c
> +++ b/arch/x86/pci/mrst.c
> @@ -141,6 +141,11 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
>   */
>  static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
>  {
> +       if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
> +                               || devfn == PCI_DEVFN(0, 0)
> +                               || devfn == PCI_DEVFN(3, 0)))
> +               return 1;

Is there any possibility of multi-function devices at bus 0, device 0, 2, or 3?

What about bridges -- can any of these be a bridge?

If either of those could happen, these checks could be too specific.

Is there a doc that identifies these cases where config mechanism #1
should be used instead of MMCONFIG?

Bjorn

> +
>         /* This is a workaround for A0 LNC bug where PCI status register does
>          * not have new CAP bit set. can not be written by SW either.
>          *
> @@ -150,10 +155,7 @@ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
>          */
>         if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
>                 return 0;
> -       if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
> -                               || devfn == PCI_DEVFN(0, 0)
> -                               || devfn == PCI_DEVFN(3, 0)))
> -               return 1;
> +
>         return 0; /* langwell on others */
>  }
>
> --
> 1.7.4.4
>
> --
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