linux-kernel - Re: [PATCH v5 01/11] mtd: add datasheet's ECC information to nand

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Message-ID: <51944184.7090107@freescale.com>
Date:	Thu, 16 May 2013 10:16:36 +0800
From:	Huang Shijie <b32955@...escale.com>
To:	<dedekind1@...il.com>
CC:	<dwmw2@...radead.org>, <computersforpeace@...il.com>,
	<linux-mtd@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 01/11] mtd: add datasheet's ECC information to nand_chip{}

于 2013年05月15日 20:11, Artem Bityutskiy 写道:
> On Wed, 2013-05-15 at 16:40 +0800, Huang Shijie wrote:
>> + * @ecc_strength:	[INTERN] ECC correctability from the datasheet.
>> + *			Minimum amount of bit errors per @ecc_step guaranteed to
>> + *			be correctable. If unknown, set to zero.
>> + * @ecc_step:		[INTERN] ECC step required by the @ecc_strength,
>> + *                      also from the datasheet. It is the recommended ECC step
>> + *			size, if known; if unknown, set to zero.
> Here and in other places you talk about "datasheet". Do you assume that
> the real ECC strength/step used by NAND chips may be different? Or you
> assume it must be the same?
>
The two fields are used to store the ecc info from the datasheet.
The two fields are just for a reference.

[1] The nand controller may do not use these two fields, it's ok;
     For example, the datasheet requires "4bits per 512 bytes".
     The nand controller can uses 8bits per 512 bytes.


[2] but sometimes the nand controller must use these two fields.
     For example, the datasheet requires "40bits per 1024 bytes".
     For the hardware limit, the nand controller(BCH) may supports the 
40bits ecc in the maximum.
     So the nand controller must use these two fields now.


thanks
Huang Shijie



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