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Message-ID: <20130524112029.GW18614@n2100.arm.linux.org.uk>
Date:	Fri, 24 May 2013 12:20:29 +0100
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	"Yang, Wenyou" <Wenyou.Yang@...el.com>
Cc:	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"plagnioj@...osoft.com" <plagnioj@...osoft.com>,
	"Ferre, Nicolas" <Nicolas.FERRE@...el.com>,
	"linux@...im.org.za" <linux@...im.org.za>
Subject: Re: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
	"MT_MEMORY_SO"

On Fri, May 24, 2013 at 07:11:04AM +0000, Yang, Wenyou wrote:
> The story is: for sama5d3x with Cortex-A5 core, if not so, when copying
> code snippet to the internal SRAM, then jump to run this code, but fail
> to run.

And that is where your mistake is - you forgot that you're working with
a CPU with harvard caches which will require some cache maintanence
between copying the code and executing it.

You want to look at flush_icache_range() rather than making this memory
strongly ordered.
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