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Message-ID: <20130524140322.GD24476@game.jcrosoft.org>
Date: Fri, 24 May 2013 16:03:22 +0200
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@...osoft.com>
To: Russell King - ARM Linux <linux@....linux.org.uk>
Cc: "Yang, Wenyou" <Wenyou.Yang@...el.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"Ferre, Nicolas" <Nicolas.FERRE@...el.com>,
"linux@...im.org.za" <linux@...im.org.za>
Subject: Re: [PATCH] ARM: at91: Fix: Change internal SRAM memory type to
"MT_MEMORY_SO"
On 12:20 Fri 24 May , Russell King - ARM Linux wrote:
> On Fri, May 24, 2013 at 07:11:04AM +0000, Yang, Wenyou wrote:
> > The story is: for sama5d3x with Cortex-A5 core, if not so, when copying
> > code snippet to the internal SRAM, then jump to run this code, but fail
> > to run.
>
> And that is where your mistake is - you forgot that you're working with
> a CPU with harvard caches which will require some cache maintanence
> between copying the code and executing it.
>
> You want to look at flush_icache_range() rather than making this memory
> strongly ordered.
I understand your point but today we map a SRAM as MT_DEVICE
I do not think it's the best
Best Regards,
J.
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