linux-kernel - Re: [PATCH 1/2] pinmux: Add TB10x pinmux driver

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Message-ID: <CAD6h2NRNMQP-ZQ0Cc613tGThVEo7AzRExBmWsbtr1DXgiPwz7w@mail.gmail.com>
Date:	Thu, 6 Jun 2013 22:32:21 +0800
From:	Haojian Zhuang <haojian.zhuang@...aro.org>
To:	Christian Ruppert <christian.ruppert@...lis.com>
Cc:	Linus Walleij <linus.walleij@...aro.org>,
	Stephen Warren <swarren@...dotorg.org>,
	Shiraz HASHIM <shiraz.hashim@...com>,
	Patrice CHOTARD <patrice.chotard@...com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Grant Likely <grant.likely@...retlab.ca>,
	Rob Herring <rob.herring@...xeda.com>,
	Rob Landley <rob@...dley.net>,
	Sascha Leuenberger <sascha.leuenberger@...lis.com>,
	Pierrick Hascoet <pierrick.hascoet@...lis.com>,
	"devicetree-discuss@...ts.ozlabs.org" 
	<devicetree-discuss@...ts.ozlabs.org>,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>
Subject: Re: [PATCH 1/2] pinmux: Add TB10x pinmux driver

On 6 June 2013 22:11, Christian Ruppert <christian.ruppert@...lis.com> wrote:
> On Wed, Jun 05, 2013 at 09:44:27AM +0800, Haojian Zhuang wrote:
>> On 3 June 2013 20:30, Christian Ruppert <christian.ruppert@...lis.com> wrote:
>> > OK, here's a simplified example of what we would like to do (this seems
>> > pretty common so I suppose there is a way I haven't understood). Our
>> > situation is slightly more complex but for the purpose of discussion
>> > let's assume a chip with 8 pins which can be configured for the
>> > following functions:
>> >
>> > Pin   GPIO-A    I2C    SPI0     SPI1
>> > ------------------------------------
>> >  1    GPIOA0    SDA             MISO1
>> >  2    GPIOA1    SCL             MOSI1
>> >  3    GPIOA2                    SS1_B
>> >  4    GPIOA3                    SCLK1
>> >  5    GPIOA4           MISO0
>> >  6    GPIOA5           MOSI0
>> >  7    GPIOA6           SS0_B
>> >  8    GPIOA7           SCLK0
>> >
>> > We can now define the following pinctrl-single:
>> >
>> > pinmux: pinmux@...FEE0000 {
>> >         compatible = "pinctrl-single";
>> >         reg = <0xFFEE0000 0x8>;
>> >         #address-cells = <1>;
>> >         #size-cells = <0>;
>> >         #gpio-range-cells = <3>;
>> >         pinctrl-single,register-width = <32>;
>> >         pinctrl-single,function-mask = <0xffffffff>;
>> >         pinctrl-single,gpio-range = <&range 1 8 0>;
>> >         gpioa_pins: pinmux_gpioa_pins {
>> >                 pinctrl-single,pins = <0x0 0 0x4 0>
>> >         };
>> >         i2c_pins: pinmux_i2c_pins {
>> >                 pinctrl-single,pins = <0x0 1>
>> >         };
>> >         spi0_pins: pinmux_spi0_pins {
>> >                 pinctrl-single,pins = <0x1 1>
>> <0x1 1>?
>>
>> If each pinmux register is only for one pin in your SoC.
>> I think that your definitions are wrong above. We use
>> register offset as the first argument, not pin number.
>> And the second argument should be pin function number.
>
> In our case each pinmux register (bit field) actually controls an entire
> group of pins.
>
>> If multiple pins are sharing one register with different bits,
>> you need to enable "pinctrl-single,bit-per-mux".
>
> Multiple pins are sharing the same bits in the same register. Do you
> think this prevents us from using pinctrl-single?
>
Could you give me your register definition? Then I can understand you
better.
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