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Message-ID: <C79B248886DD134989C8FF6B096A91AB91B616BEF3@BGMAIL01.nvidia.com>
Date: Tue, 11 Jun 2013 16:10:43 +0530
From: Jay Agarwal <jagarwal@...dia.com>
To: 'Thierry Reding' <thierry.reding@...il.com>
CC: Stephen Warren <swarren@...dotorg.org>,
"linux@....linux.org.uk" <linux@....linux.org.uk>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
Laxman Dewangan <ldewangan@...dia.com>,
"olof@...om.net" <olof@...om.net>, Hiroshi Doyu <hdoyu@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
"mturquette@...aro.org" <mturquette@...aro.org>,
Peter De Schrijver <pdeschrijver@...dia.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
Juha Tukkinen <jtukkinen@...dia.com>,
Krishna Thota <kthota@...dia.com>
Subject: RE: [PATCH V3 2/4] ARM: tegra: pcie: Add tegra3 support
> > I have mentioned it in description as -> "Corrected logic in read/write
> config space to display right device number on bus 0"
> >
> > > Device 0:00.0 is usually the root complex, and device 0:01.0, 0:02.0
> > > etc are the root ports. The change proposed above makes 0:00.0 the
> > > first root port, therefore breaking what systems usually expect.
> > >
> > I was seeing root port 2 in cardhu being enumerated as pci_bus 0000:03,
> which I thought should be pci_bus 0000:02, so made this change.
>
> Yes, that's done on purpose to mirror what a typical PCI tree looks like, as I
> already explained. So unless this fixes a real bug I'll just drop it while
> applying.
Please apply V4 patch instead which does not contain this change along with taking care of other review comments.
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