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Message-ID: <1563709.AX9HNR4mCI@flatron>
Date: Thu, 13 Jun 2013 13:03:12 +0200
From: Tomasz Figa <tomasz.figa@...il.com>
To: Doug Anderson <dianders@...omium.org>
Cc: Linus Walleij <linus.walleij@...aro.org>,
Kukjin Kim <kgene.kim@...sung.com>,
Olof Johansson <olof@...om.net>,
Simon Glass <sjg@...omium.org>,
Luigi Semenzato <semenzato@...omium.org>,
ilho215.lee@...sung.com, eunki_kim@...sung.com,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3] pinctrl: exynos: Add spinlocks to irq_mask and irq_unmask
Hi Doug,
On Wednesday 12 of June 2013 10:33:17 Doug Anderson wrote:
> The patch:
> 1984695 pinctrl: samsung: Protect bank registers with a spinlock
>
> ...added spinlocks to protect many accesses. However, the irq_mask
> and irq_unmask functions still do an unprotected read/modify/write.
> Add the spinlock there.
Right, that's correct.
I always thought that the IRQ core already does some irqchip level
locking, but it seems like I got confused by irq_desc spinlock. Thanks for
spotting this.
Acked-by: Tomasz Figa <t.figa@...sung.com>
Best regards,
Tomasz
> Signed-off-by: Doug Anderson <dianders@...omium.org>
> ---
> drivers/pinctrl/pinctrl-exynos.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-exynos.c
> b/drivers/pinctrl/pinctrl-exynos.c index 2d76f66..c29a28e 100644
> --- a/drivers/pinctrl/pinctrl-exynos.c
> +++ b/drivers/pinctrl/pinctrl-exynos.c
> @@ -56,10 +56,15 @@ static void exynos_gpio_irq_unmask(struct irq_data
> *irqd) struct samsung_pinctrl_drv_data *d = bank->drvdata;
> unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
> unsigned long mask;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&bank->slock, flags);
>
> mask = readl(d->virt_base + reg_mask);
> mask &= ~(1 << irqd->hwirq);
> writel(mask, d->virt_base + reg_mask);
> +
> + spin_unlock_irqrestore(&bank->slock, flags);
> }
>
> static void exynos_gpio_irq_mask(struct irq_data *irqd)
> @@ -68,10 +73,15 @@ static void exynos_gpio_irq_mask(struct irq_data
> *irqd) struct samsung_pinctrl_drv_data *d = bank->drvdata;
> unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
> unsigned long mask;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&bank->slock, flags);
>
> mask = readl(d->virt_base + reg_mask);
> mask |= 1 << irqd->hwirq;
> writel(mask, d->virt_base + reg_mask);
> +
> + spin_unlock_irqrestore(&bank->slock, flags);
> }
>
> static void exynos_gpio_irq_ack(struct irq_data *irqd)
> @@ -264,10 +274,15 @@ static void exynos_wkup_irq_unmask(struct irq_data
> *irqd) struct samsung_pinctrl_drv_data *d = b->drvdata;
> unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
> unsigned long mask;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&b->slock, flags);
>
> mask = readl(d->virt_base + reg_mask);
> mask &= ~(1 << irqd->hwirq);
> writel(mask, d->virt_base + reg_mask);
> +
> + spin_unlock_irqrestore(&b->slock, flags);
> }
>
> static void exynos_wkup_irq_mask(struct irq_data *irqd)
> @@ -276,10 +291,15 @@ static void exynos_wkup_irq_mask(struct irq_data
> *irqd) struct samsung_pinctrl_drv_data *d = b->drvdata;
> unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
> unsigned long mask;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&b->slock, flags);
>
> mask = readl(d->virt_base + reg_mask);
> mask |= 1 << irqd->hwirq;
> writel(mask, d->virt_base + reg_mask);
> +
> + spin_unlock_irqrestore(&b->slock, flags);
> }
>
> static void exynos_wkup_irq_ack(struct irq_data *irqd)
--
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