linux-kernel - Re: [PATCH v2 4/7] perf, x86: Save/resotre LBR stack during context switch

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Message-ID: <20130704134457.GS6123@two.firstfloor.org>
Date:	Thu, 4 Jul 2013 15:44:57 +0200
From:	Andi Kleen <andi@...stfloor.org>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	"Yan, Zheng" <zheng.z.yan@...el.com>, linux-kernel@...r.kernel.org,
	mingo@...nel.org, eranian@...gle.com, andi@...stfloor.org
Subject: Re: [PATCH v2 4/7] perf, x86: Save/resotre LBR stack during
 context switch

On Thu, Jul 04, 2013 at 11:57:35AM +0200, Peter Zijlstra wrote:
> On Mon, Jul 01, 2013 at 03:23:04PM +0800, Yan, Zheng wrote:
> > +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> > @@ -185,6 +185,13 @@ void intel_pmu_lbr_reset(void)
> >  		intel_pmu_lbr_reset_32();
> >  	else
> >  		intel_pmu_lbr_reset_64();
> > +
> > +	wrmsrl(x86_pmu.lbr_tos, 0);
> > +}
> 
> I double checked; my SDM Jun 2013, Vol 3C 35-93 very explicitly states that
> MSR_LASTBRANCH_TOS is a read-only MSR. And afaicr all previous times I checked
> this it did say this too.

Evidently it's not read-only on Haswell at least.

And if we don't restore the TOS it can be completely wrong, and
the stack state would corrupt.

The LBR stack is quite sensitive to any corruption of the state,
that is different from other LBR uses.

I suppose the wrmsr could be made checking to catch any potential
failure. But normally Intel CPUs are quite consistent in things
like that.

-Andi

-- 
ak@...ux.intel.com -- Speaking for myself only.
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