linux-kernel - Re: [PATCH v2 4/7] perf, x86: Save/resotre LBR stack during context switch

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Message-ID: <20130704140057.GN18898@dyad.programming.kicks-ass.net>
Date:	Thu, 4 Jul 2013 16:00:57 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	Andi Kleen <andi@...stfloor.org>
Cc:	"Yan, Zheng" <zheng.z.yan@...el.com>, linux-kernel@...r.kernel.org,
	mingo@...nel.org, eranian@...gle.com
Subject: Re: [PATCH v2 4/7] perf, x86: Save/resotre LBR stack during context
 switch

On Thu, Jul 04, 2013 at 03:44:57PM +0200, Andi Kleen wrote:
> Evidently it's not read-only on Haswell at least.

It would be ever so good if you could at least test run such patches against
semi-current chips, not only the very latest.

> And if we don't restore the TOS it can be completely wrong, and
> the stack state would corrupt.

How so? You could simply write into idx := (tos + i) % nr_lbr ?

> The LBR stack is quite sensitive to any corruption of the state,
> that is different from other LBR uses.
> 
> I suppose the wrmsr could be made checking to catch any potential
> failure. But normally Intel CPUs are quite consistent in things
> like that.

Please verify with the appropriate hardware teams and update the SDM
accordingly. This code is used with all Intel CPUs that have LBR support, which
is pretty much all of them except Yonah.

Using a checking wmsr isn't really a nice option; esp as this is in a somewhat
time critical path.

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