linux-kernel - Re: [RFC] [PATCH 1/2 v2] x86: introduce int3-based instruction patching

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Message-ID: <51DF1AB9.2010405@linux.intel.com>
Date:	Thu, 11 Jul 2013 13:51:05 -0700
From:	"H. Peter Anvin" <hpa@...ux.intel.com>
To:	Jiri Kosina <jkosina@...e.cz>
CC:	Masami Hiramatsu <masami.hiramatsu.pt@...achi.com>,
	Steven Rostedt <rostedt@...dmis.org>,
	Jason Baron <jbaron@...hat.com>,
	Borislav Petkov <bpetkov@...e.de>, linux-kernel@...r.kernel.org
Subject: Re: [RFC] [PATCH 1/2 v2] x86: introduce int3-based instruction patching

On 07/11/2013 12:29 PM, Jiri Kosina wrote:
> On Thu, 11 Jul 2013, H. Peter Anvin wrote:
> 
>>>> + * The way it is done:
>>>> + *	- add a int3 trap to the address that will be patched
>>>> + *	- sync cores
>>>
>>> You don't need this "sync cores". (and your code didn't) :)
>>
>> I believe you do, lest you get "Frankenstructions".  I believe you don't
>> need the second one, however.  I should dig up my notes on this.
> 
> I found this post from 2010 from you:
> 
> 	http://lkml.indiana.edu/hypermail/linux/kernel/1001.1/01530.html
> 
> If it's still valid and you guys at Intel haven't discovered any reason 
> why that procedure would be invalid, I'll send out v3 with that'd be using 
> exactly this ordering of syncing of the cores.
> 

Just a note on that: in that post "In fact, if a suitable int3 handler
is left permanently in place then step 5 is unnecessary as well" should
obviously have been "the synchronization in step 4" rather than "step 5".

	-hpa

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