linux-kernel - RE: [PATCH v8 06/12] ARM: dts: Add description of System MMU of Exynos SoCs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Wed, 07 Aug 2013 21:07:01 +0900
From:	Cho KyongHo <pullip.cho@...sung.com>
To:	'Grant Grundler' <grundler@...omium.org>,
	'Marek Szyprowski' <m.szyprowski@...sung.com>
Cc:	'Bartlomiej Zolnierkiewicz' <b.zolnierkie@...sung.com>,
	'Linux ARM Kernel' <linux-arm-kernel@...ts.infradead.org>,
	'Linux IOMMU' <iommu@...ts.linux-foundation.org>,
	'Linux Kernel' <linux-kernel@...r.kernel.org>,
	'Linux Samsung SOC' <linux-samsung-soc@...r.kernel.org>,
	'Hyunwoong Kim' <khw0178.kim@...sung.com>,
	'Joerg Roedel' <joro@...tes.org>,
	'Kukjin Kim' <kgene.kim@...sung.com>,
	'Prathyush' <prathyush.k@...sung.com>,
	'Rahul Sharma' <rahul.sharma@...sung.com>,
	'Subash Patel' <supash.ramaswamy@...aro.org>,
	'Keyyoung Park' <keyyoung.park@...sung.com>,
	'Antonios Motakis' <a.motakis@...tualopensystems.com>,
	kvmarm@...ts.cs.columbia.edu,
	'Sachin Kamat' <sachin.kamat@...aro.org>
Subject: RE: [PATCH v8 06/12] ARM: dts: Add description of System MMU of Exynos
 SoCs

> -----Original Message-----
> From: grundler@...gle.com [mailto:grundler@...gle.com] On Behalf Of Grant Grundler
> Sent: Wednesday, August 07, 2013 1:07 AM
> To: Marek Szyprowski
> 
> Hi Marek,
> 
> On Tue, Aug 6, 2013 at 6:17 AM, Marek Szyprowski
> <m.szyprowski@...sung.com> wrote:
> ...
> > IMHO it is much better to have a simple driver, which binds to a single
> > IOMMU controller and leave it to the driver whether to have a same virtual address
> > space for all parts of FIMC-IS or MFC submodules/memory ports or not.
> 
> I understand this part. I having written the IOMMU support for 4
> different IOMMUs, all of which had exactly one IO Page Table and one
> IOMMU shared by many devices.
> 
> > Just make sure that it will be possible to attach more than one sysmmu
> > controller to one iommu domain.
> 
> I don't understand how this is possible. Can someone explain this
> better in the IOMMU documentation please?

System MMU is dedicated to a master H/W such as FIMD and FIMC.
Thus, attaching a master H/W to an iommu domain can be thought as
attaching a System MMU to an iommu domain even though such thinking
is not correct view of the relationship between iommu domain and
System MMU.

> 
> "iommu domain" to me means one virtual IO address space for attached
> devices that can master DMA transactions. The IOMMU then uses it's IO
> Page Table to translate the DMA address to the system physical address
> space and forwards the transaction.
> 
> What is the role of the sysmmu in all of this?
> Is the sysmmu just the MMU (or collection of MMU) for host DRAM?
> Or is sysmmu responsible for "other stuff"? (clocks, power domains, MMU, etc)
> 
System MMU is responsible for address translation of traffic from a
master H/W which the System MMU is dedicated to.

> I can understand we might have multiple MMUs in a system...e.g. every
> range of memory might have it's own MMU. But they share the same
> physical address space and generally live under one page table.
> Because of "one page table" I would consider them one entity from the
> the IOMMUs perspective.

Sorry, I don't understand.
Do you mean you are thinking that it is better to share one page table
by all IOMMUs in a system?

Thank you,
KyongHo
> 
> thanks,
> grant

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/