Message-ID: <CANEJEGtDm6FYvx8DdiGofk5ViU8kWK-3QvTvtU66Mvhfn+sDCQ@mail.gmail.com>
Date:	Wed, 7 Aug 2013 09:21:07 -0700
From:	Grant Grundler <grundler@...omium.org>
To:	Cho KyongHo <pullip.cho@...sung.com>
Cc:	Grant Grundler <grundler@...omium.org>,
	Marek Szyprowski <m.szyprowski@...sung.com>,
	Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>,
	Linux ARM Kernel <linux-arm-kernel@...ts.infradead.org>,
	Linux IOMMU <iommu@...ts.linux-foundation.org>,
	Linux Kernel <linux-kernel@...r.kernel.org>,
	Linux Samsung SOC <linux-samsung-soc@...r.kernel.org>,
	Hyunwoong Kim <khw0178.kim@...sung.com>,
	Joerg Roedel <joro@...tes.org>,
	Kukjin Kim <kgene.kim@...sung.com>,
	Prathyush <prathyush.k@...sung.com>,
	Rahul Sharma <rahul.sharma@...sung.com>,
	Subash Patel <supash.ramaswamy@...aro.org>,
	Keyyoung Park <keyyoung.park@...sung.com>,
	Antonios Motakis <a.motakis@...tualopensystems.com>,
	kvmarm@...ts.cs.columbia.edu,
	Sachin Kamat <sachin.kamat@...aro.org>
Subject: Re: [PATCH v8 06/12] ARM: dts: Add description of System MMU of
 Exynos SoCs

On Wed, Aug 7, 2013 at 5:07 AM, Cho KyongHo <pullip.cho@...sung.com> wrote:
...
>> I don't understand how this is possible. Can someone explain this
>> better in the IOMMU documentation please?
>
> System MMU is dedicated to a master H/W such as FIMD and FIMC.

Sory - Exynos 5250 documentation I have (confidential version) uses
FIMD and FIMC but never explains what they are nor identifies them in
a diagram. Based on the references, they are related to the video
mixer but I don't know exactly what function FIMD/FIMC serve.


> Thus, attaching a master H/W to an iommu domain can be thought as
> attaching a System MMU to an iommu domain even though such thinking
> is not correct view of the relationship between iommu domain and
> System MMU.

This almost makes sense. I understand the above to mean the System MMU
is a proxy for the FIMD and FIMC.

>> I can understand we might have multiple MMUs in a system...e.g. every
>> range of memory might have it's own MMU. But they share the same
>> physical address space and generally live under one page table.
>> Because of "one page table" I would consider them one entity from the
>> the IOMMUs perspective.
>
> Sorry, I don't understand.
> Do you mean you are thinking that it is better to share one page table
> by all IOMMUs in a system?

No. This is how the previous IOMMUs I worked on functioned. It doesn't
mean this is how current ones should.

My example above was referring to CPU MMUs in the case of NUMA
architectures. Each NUMA CPU socket can have it's own MMU (and TLB)
and corresponding memory controller. All CPUs in an SMP system map
process and kernel virtual addresses to one common "physical" address
space. This means allocation and use of "physical address space" has
to be managed as one entity (even if several page tables exist in the
implementation - e.g. NUMA).


Back to the original comment that started my question (pulled out of
context now...sorry):
   "Just make sure that it will be possible to attach more than one
sysmmu controller to one iommu domain."

Does that mean the IOMMU now has to map to multiple "physical address
spaces" or am I completely missing what a SysMMU does?

The "SysMMU" is the System Memory Management Unit, right?

I still thinking one IOMMU domain maps one (IO) virtual address space
to one (common with CPU and other IOMMU) physical address space.

cheers,
grant

>
> Thank you,
> KyongHo
>>
>> thanks,
>> grant
>
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