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Message-id: <002501ce9324$8066f5a0$8134e0e0$@samsung.com>
Date: Wed, 07 Aug 2013 13:13:42 +0900
From: Jingoo Han <jg1.han@...sung.com>
To: 'Bjorn Helgaas' <bhelgaas@...gle.com>
Cc: linux-pci@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
'Kukjin Kim' <kgene.kim@...sung.com>,
'Pratyush Anand' <pratyush.anand@...com>,
'Mohit KUMAR' <Mohit.KUMAR@...com>,
'Arnd Bergmann' <arnd@...db.de>,
'Sean Cross' <xobs@...agi.com>,
'Kishon Vijay Abraham I' <kishon@...com>,
'Thierry Reding' <thierry.reding@...il.com>,
'SRIKANTH TUMKUR SHIVANAND' <ts.srikanth@...sung.com>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Jingoo Han <jg1.han@...sung.com>
Subject: Re: [PATCH V5] pci: exynos: split into two parts such as Synopsys part
and Exynos part
On Wednesday, July 31, 2013 5:14 PM, Jingoo Han <jg1.han@...sung.com> wrote:
> Exynos PCIe IP consists of Synopsys specific part and Exynos
> specific part. Only core block is a Synopsys designware part;
> other parts are Exynos specific.
> Also, the Synopsys designware part can be shared with other
> platforms; thus, it can be split two parts such as Synopsys
> designware part and Exynos specific part.
>
> Signed-off-by: Jingoo Han <jg1.han@...sung.com>
> Cc: Pratyush Anand <pratyush.anand@...com>
> Cc: Mohit KUMAR <Mohit.KUMAR@...com>
Hi Bjorn Helgaas,
There is no comment for last 2 weeks.
Will you accept this patch?
Best regards,
Jingoo Han
> ---
> Changes since v4:
> - fixed section mismatch warnings
> - fixed sparse warnings
>
> .../devicetree/bindings/pci/designware-pcie.txt | 3 +
> arch/arm/boot/dts/exynos5440.dtsi | 2 +
> drivers/pci/host/Makefile | 3 +-
> drivers/pci/host/pci-exynos.c | 530 ++++++++++
> drivers/pci/host/pcie-designware.c | 1011 ++++++--------------
> drivers/pci/host/pcie-designware.h | 65 ++
> 6 files changed, 874 insertions(+), 740 deletions(-)
> create mode 100644 drivers/pci/host/pci-exynos.c
> create mode 100644 drivers/pci/host/pcie-designware.h
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