linux-kernel - Re: [PATCH] PCI: exynos: add support for MSI

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Date:	Mon, 12 Aug 2013 17:17:22 +0530
From:	Pratyush Anand <pratyush.anand@...com>
To:	Thierry Reding <thierry.reding@...il.com>,
	Jingoo Han <jg1.han@...sung.com>
Cc:	Bjorn Helgaas <bhelgaas@...gle.com>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-samsung-soc@...r.kernel.org" 
	<linux-samsung-soc@...r.kernel.org>,
	Kukjin Kim <kgene.kim@...sung.com>,
	Mohit KUMAR DCG <Mohit.KUMAR@...com>,
	Siva Reddy Kallam <siva.kallam@...sung.com>,
	'SRIKANTH TUMKUR SHIVANAND' <ts.srikanth@...sung.com>,
	Arnd Bergmann <arnd@...db.de>, 'Sean Cross' <xobs@...agi.com>,
	'Kishon Vijay Abraham I' <kishon@...com>,
	'Thomas Petazzoni' <thomas.petazzoni@...e-electrons.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH] PCI: exynos: add support for MSI

On Mon, Aug 12, 2013 at 06:56:40PM +0800, Thierry Reding wrote:
> On Mon, Aug 12, 2013 at 05:56:47PM +0900, Jingoo Han wrote:
> [...]
> > diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> > index 855d4a7..9ef1c95 100644
> > --- a/arch/arm/mach-exynos/Kconfig
> > +++ b/arch/arm/mach-exynos/Kconfig
> > @@ -93,6 +93,7 @@ config SOC_EXYNOS5440
> >  	default y
> >  	depends on ARCH_EXYNOS5
> >  	select ARCH_HAS_OPP
> > +	select ARCH_SUPPORTS_MSI
> 
> This symbol goes away in Thomas Petazzoni's MSI patch series which is
> targetted at 3.12, so I don't think you should add that here.
> 
> > +#ifdef CONFIG_PCI_MSI
> > +static void exynos_pcie_clear_irq_level(struct pcie_port *pp)
> > +{
> > +	u32 val;
> > +	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > +	void __iomem *elbi_base = exynos_pcie->elbi_base;
> > +
> > +	val = readl(elbi_base + PCIE_IRQ_LEVEL);
> > +	writel(val, elbi_base + PCIE_IRQ_LEVEL);
> > +	return;
> > +}
> 
> I'm a little confused by this: the above code seems to access the PCIe
> controller registers to clear an interrupt, but you pass in a PCIe
> port...
> 

One struct pcie_port is associated with one controller and it has been
assumed that there is only one root port per controller. 

[...]

> > +void dw_pcie_msi_init(struct pcie_port *pp)
> > +{
> > +	/* program the msi_data */
> > +	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
> > +			__virt_to_phys((u32)(&msi_data)));
> 
> That's slightly odd. You convert the virtual address of a local variable
> (local to the file) to a physical address and program that into a
> register. I assume that it works since you've probably tested this, but
> I wonder if it's safe to do this. Perhaps a better way would be to
> allocate a single free page (__get_free_pages(GFP_KERNEL, 0)) and write
> the physical address of that into the register instead.
> 

also msi_data must be different for different controller. Something
like &msi_data[pp->port].

[...]

> > +void arch_teardown_msi_irq(unsigned int irq)
> > +{
> > +	clear_irq(irq);
> > +}
> 
> And we've reworked this largely so that drivers no longer provide arch_*
> functions because that prevents multi-platform support. So I think you
> need to port this to the new msi_chip infrastructure that's being
> introduced in 3.12.

Yes, its needed.

Regards
Pratyush

> 
> Thierry


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