linux-kernel - Re: linux-next: manual merge of the clk tree with Linus' tree

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Date:	Wed, 28 Aug 2013 17:22:25 +1000
From:	Stephen Rothwell <sfr@...b.auug.org.au>
To:	Mike Turquette <mturquette@...aro.org>
Cc:	Sören Brinkmann <soren.brinkmann@...inx.com>,
	James Hogan <james.hogan@...tec.com>,
	<linux-next@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	Michal Simek <michal.simek@...inx.com>
Subject: Re: linux-next: manual merge of the clk tree with Linus' tree

Hi all,

On Wed, 28 Aug 2013 10:04:31 +1000 Stephen Rothwell <sfr@...b.auug.org.au> wrote:
>
> On Tue, 27 Aug 2013 09:53:19 -0700 Mike Turquette <mturquette@...aro.org> wrote:
> >
> > Quoting Sören Brinkmann (2013-08-27 08:44:11)
> > > On Tue, Aug 27, 2013 at 11:09:52AM +0100, James Hogan wrote:
> > > > On 27/08/13 10:03, Stephen Rothwell wrote:
> > > > > Hi Mike,
> > > > > 
> > > > > Today's linux-next merge of the clk tree got a conflict in
> > > > > drivers/clk/zynq/clkc.c between commits 252957cc3a2d ("clk/zynq/clkc: Add
> > > > > dedicated spinlock for the SWDT") and 765b7d4c4cb3
> > > > > ("clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes") from
> > > > > Linus' tree and commit 819c1de344c5 ("clk: add CLK_SET_RATE_NO_REPARENT
> > > > > flag") from the clk tree.
> > > > > 
> > > > > I fixed it up (see below and in a couple of places I chose
> > > > > CLK_SET_RATE_NO_REPARENT over CLK_SET_RATE_PARENT, which may, of course,
> > > > > be wrong) and can carry the fix as necessary (no action is required).
> > > > 
> > > > The case you mentioned looks correct to me.
> > > > 
> > > > I can't see todays -next yet, but if by "choose CLK_SET_RATE_NO_REPARENT
> > > > over CLK_SET_RATE_PARENT" you mean one branch adds CLK_SET_RATE_PARENT,
> > > > clk-next adds CLK_SET_RATE_NO_REPARENT, and the resolution ends up with
> > > > only CLK_SET_RATE_NOREPARENT then that sounds wrong, as the two flags
> > > > are orthogonal.
> > > 
> > > I can just agree, the case included in the mail looks correct, but in
> > > case of other conflicts both flags should be set. Just like in the case
> > > shown here.
> > 
> > Stephen's fix is correct. The Zynq patches came in as fixes so I think
> > this will be a rare event.
> 
> Can you guys discuss this and come up with a single answer.  I read the above as:
> 
> (for the two places I used CLK_SET_RATE_NO_REPARENT where the two
> branches each added that and CLK_SET_RATE_NOREPARENT respectively)
> 
> "Stephen was wrong"
> "Stephen should have taken both"
> "Stephen was right"
> 
> :-)
> 
> I can fix up my merge resolution if you tell me the correct fix.  Also,
> you will need to know so that you can tell Linus (or whoever else has to
> resolve these conflicts).

OK, I thought about it some more and the resolution now looks like
below.  Is this correct/better?

-- 
Cheers,
Stephen Rothwell                    sfr@...b.auug.org.au

6c92037c7a4574c16bc86873fe603b39b7fbe98a
diff --cc drivers/clk/zynq/clkc.c
index 089d3e3,e05c9e3..6f104db
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@@ -293,8 -294,9 +295,9 @@@ static void __init zynq_clk_setup(struc
  			swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
  	}
  	clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
- 			swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT,
- 			SLCR_SWDT_CLK_SEL, 0, 1, 0, &swdtclk_lock);
+ 			swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
+ 			CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
 -			&gem0clk_lock);
++			&swdtclk_lock);
  
  	/* DDR clocks */
  	clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
@@@ -366,8 -369,8 +370,8 @@@
  			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
  			&gem0clk_lock);
  	clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
- 			CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0,
 -			CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0,
--			&gem0clk_lock);
++			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++			SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock);
  	clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
  			"gem0_emio_mux", CLK_SET_RATE_PARENT,
  			SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
@@@ -389,8 -393,8 +394,8 @@@
  			CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
  			&gem1clk_lock);
  	clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
- 			CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0,
 -			CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0,
--			&gem1clk_lock);
++			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++			SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock);
  	clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
  			"gem1_emio_mux", CLK_SET_RATE_PARENT,
  			SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);

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