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Message-ID: <CAK9yfHzb8VA+E38iQ3b31Yjfd9BvKcEMBc_gijJ3hERa_fBqFw@mail.gmail.com>
Date: Wed, 25 Sep 2013 17:05:11 +0530
From: Sachin Kamat <sachin.kamat@...aro.org>
To: Lukasz Majewski <l.majewski@...sung.com>
Cc: "Rafael J. Wysocki" <rjw@...k.pl>,
Viresh Kumar <viresh.kumar@...aro.org>,
Linux PM list <linux-pm@...r.kernel.org>,
Lukasz Majewski <l.majewski@...ess.pl>,
linux-kernel <linux-kernel@...r.kernel.org>,
Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>,
Tomasz Figa <t.figa@...sung.com>,
Myungjoo Ham <myungjoo.ham@...sung.com>,
Kukjin Kim <kgene@...nel.org>,
Kukjin Kim <kgene.kim@...sung.com>,
linux-samsung-soc <linux-samsung-soc@...r.kernel.org>
Subject: Re: [PATCH 1/2] cpufreq: exynos4x12: Use the common clock framework
to set APLL clock rate
Hi Lukasz,
On 25 September 2013 16:52, Lukasz Majewski <l.majewski@...sung.com> wrote:
>
> static void exynos4x12_set_apll(unsigned int index)
> {
> - unsigned int tmp, pdiv;
> + unsigned int tmp, freq = apll_freq_4x12[index].freq;
nit: It is better to put the 'freq' assignment on a new line.
>
> - /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
> + /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
> clk_set_parent(moutcore, mout_mpll);
>
> do {
> @@ -140,24 +140,9 @@ static void exynos4x12_set_apll(unsigned int index)
> tmp &= 0x7;
> } while (tmp != 0x2);
>
> - /* 2. Set APLL Lock time */
> - pdiv = ((apll_freq_4x12[index].mps >> 8) & 0x3f);
> + clk_set_rate(mout_apll, freq * 1000);
Don't we need to check the return value of this?
Same comments for the second patch too.
--
With warm regards,
Sachin
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