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Message-ID: <20131028104505.GB2278@thinkpad.fritz.box> Date: Mon, 28 Oct 2013 11:45:05 +0100 From: Andreas Werner <wernerandy@....de> To: Ingo Molnar <mingo@...nel.org> Cc: Borislav Petkov <bp@...en8.de>, tglx@...utronix.de, mingo@...hat.com, hpa@...or.com, x86@...nel.org, dave@...ux.vnet.ibm.com, linux-kernel@...r.kernel.org Subject: Re: [PATCH] X86: MM: Add PAT Type write-through in combination with mtrr On Mon, Oct 28, 2013 at 11:31:32AM +0100, Ingo Molnar wrote: > > * Borislav Petkov <bp@...en8.de> wrote: > > > On Mon, Oct 28, 2013 at 11:17:49AM +0100, Ingo Molnar wrote: > > > > > And regular write-back cacheable isn't sufficient because the > > > CPU could do things like prefetch your range automatically? > > > > Yeah, he's doing a CLFLUSH anyway which basically makes it a > > write-through... > > The CLFLUSH is done afterwards (making it a use-once thing), so WB > might still be faster and would avoid the PAT headache ... > > Thanks, > > Ingo What i do right now is: 1. clflush the data range to read from my mmio device 2. read the data. On PCIe Tracer i see the pcie bursts. If i mark the region WB and call clflush my system will crash without any message, it just stop working. regards Andy -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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