linux-kernel - ARM GIC Virtualization question

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Message-ID: <CAPUj1ONAa+6AjR9APOhi=QpmKJY6afpmsPvVcb3ecApBj_pRJg@mail.gmail.com>
Date:	Mon, 28 Oct 2013 12:54:57 +0530
From:	Mj Embd <mj.embd@...il.com>
To:	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	linaro-kernel <linaro-kernel@...ts.linaro.org>,
	Simon Glass <sjg@...omium.org>
Subject: ARM GIC Virtualization question

Hi All,

a) As per GIC-400 all Physical interrupts trap into hypervisor
b) Hypervisor does ACK, programs Virtual GIC list registers (with
PhysIRQ:VIRQ) and does a world switch.
c) GIC CPU I/f interrupts Guest with the VIRQ
d) Guest does a ACK and EOI to GIC cpu i/f
e) Hypervisor gets a maintenance interrupt when Guest Does an EOI
f) Hypervisor then clears the Physical Interrupt

So for 1 interrupt there are so many context switches ? Is the
sequence right. If I am missing anything please let me know ..

Also, If a device is private to a guest, so many context switches
would reduce the performance if the device interrupts a lot.

My question is that
a) Is the above flow correct ?
b) Is this the only flow or there exists some optimisations

Thanks and Regards
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