lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:	Thu, 31 Oct 2013 09:32:51 -0500
From:	Kumar Gala <galak@...eaurora.org>
To:	Sricharan R <r.sricharan@...com>
Cc:	<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
	<linux-doc@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-omap@...r.kernel.org>, <linus.walleij@...aro.org>,
	<linux@....linux.org.uk>, <tony@...mide.com>, <rnayak@...com>,
	<marc.zyngier@....com>, <grant.likely@...aro.org>,
	<mark.rutland@....com>, <robherring2@...il.com>,
	<tglx@...utronix.de>, <santosh.shilimkar@...com>,
	Rob Herring <rob.herring@...xeda.com>
Subject: Re: [PATCH V2 1/7] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs


On Oct 30, 2013, at 9:57 AM, Sricharan R wrote:

> In some socs the gic can be preceded by a crossbar IP which
> routes the peripheral interrupts to the gic inputs. The peripheral
> interrupts are associated with a fixed crossbar input line and the
> crossbar routes that to one of the free gic input line.
> 
> The DT entries for peripherals provides the fixed crossbar input line
> as its interrupt number and the mapping code should associate this with
> a free gic input line. This patch adds the support inside the gic irqchip
> to handle such routable irqs. The routable irqs are registered in a linear
> domain. The registered routable domain's callback should be implemented
> to get a free irq and to configure the IP to route it.
> 
> Cc: Thomas Gleixner <tglx@...utronix.de>
> Cc: Linus Walleij <linus.walleij@...aro.org>
> Cc: Santosh Shilimkar <santosh.shilimkar@...com>
> Cc: Russell King <linux@....linux.org.uk>
> Cc: Tony Lindgren <tony@...mide.com>
> Cc: Rajendra Nayak <rnayak@...com>
> Cc: Marc Zyngier <marc.zyngier@....com>
> Cc: Grant Likely <grant.likely@...aro.org>
> Cc: Rob Herring <rob.herring@...xeda.com>
> Signed-off-by: Sricharan R <r.sricharan@...com>
> ---
> [V2] Added default routable-irqs functions to avoid
>      unnessecary if checks as per Thomas Gleixner comments
>      and renamed routable-irq binding as per
>      Kumar Gala <galak@...eaurora.org> comments.
> 
> Documentation/devicetree/bindings/arm/gic.txt |    6 ++
> drivers/irqchip/irq-gic.c                     |   83 ++++++++++++++++++++++---
> include/linux/irqchip/arm-gic.h               |    8 ++-
> 3 files changed, 87 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
> index 3dfb0c0..5357745 100644
> --- a/Documentation/devicetree/bindings/arm/gic.txt
> +++ b/Documentation/devicetree/bindings/arm/gic.txt
> @@ -49,6 +49,11 @@ Optional
>   regions, used when the GIC doesn't have banked registers. The offset is
>   cpu-offset * cpu-nr.
> 
> +- arm,routable-irqs : Total number of gic irq inputs which are not directly
> +		  connected from the peripherals, but are routed dynamically
> +		  by a crossbar/multiplexer preceding the GIC. The GIC irq
> +		  input line is assigned dynamically when the corresponding
> +		  peripheral's crossbar line is mapped.
> Example:
> 
> 	intc: interrupt-controller@...11000 {
> @@ -56,6 +61,7 @@ Example:
> 		#interrupt-cells = <3>;
> 		#address-cells = <1>;
> 		interrupt-controller;
> +		arm,routable-irqs = <160>;
> 		reg = <0xfff11000 0x1000>,
> 		      <0xfff10100 0x100>;
> 	};

DT Binding portion:

Acked-by: Kumar Gala <galak@...eaurora.org>

- k

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ