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Message-Id: <1388105067-24438-7-git-send-email-abrestic@chromium.org>
Date: Thu, 26 Dec 2013 16:44:26 -0800
From: Andrew Bresticker <abrestic@...omium.org>
To: Mike Turquette <mturquette@...aro.org>,
Stephen Warren <swarren@...dotorg.org>
Cc: Thierry Reding <thierry.reding@...il.com>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Andrew Bresticker <abrestic@...omium.org>
Subject: [PATCH 6/7] clk: tegra: cclk_lp has a pllx/2 divider
When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines
whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that
the clk_super driver is aware of this.
Signed-off-by: Andrew Bresticker <abrestic@...omium.org>
---
drivers/clk/tegra/clk-tegra-super-gen4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
index 05dce4a..feb3201 100644
--- a/drivers/clk/tegra/clk-tegra-super-gen4.c
+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
@@ -120,7 +120,7 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
ARRAY_SIZE(cclk_lp_parents),
CLK_SET_RATE_PARENT,
clk_base + CCLKLP_BURST_POLICY,
- 0, 4, 8, 9, NULL);
+ TEGRA_DIVIDER_2, 4, 8, 9, NULL);
*dt_clk = clk;
}
--
1.8.5.1
--
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