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Message-ID: <20140115183822.GC28782@mudshark.cambridge.arm.com>
Date: Wed, 15 Jan 2014 18:38:22 +0000
From: Will Deacon <will.deacon@....com>
To: Vince Weaver <vincent.weaver@...ne.edu>
Cc: Chad Paradis <chad.paradis@...t.maine.edu>,
Peter Zijlstra <peterz@...radead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Paul Mackerras <paulus@...ba.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
Stephane Eranian <eranian@...il.com>
Subject: Re: [patch/rfc] perf on raspberry-pi without overflow interrupt
Hi Vince,
On Tue, Jan 14, 2014 at 04:42:13AM +0000, Vince Weaver wrote:
> On Fri, 10 Jan 2014, Will Deacon wrote:
> > In the absence of a core change, I think I'd rather have something like your
> > second patch, but without the extra no_overflow_irq field (you can check the
> > platform device, as I mentioned previously).
>
> Something like the following? It works on my rasp-pi, still waiting for
> the compile to finish on the pandaboard so I haven't verified that the
> has-working-interrupt case still works.
[...]
> diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
> index bc3f2ef..e2c4aa2 100644
> --- a/arch/arm/kernel/perf_event.c
> +++ b/arch/arm/kernel/perf_event.c
> @@ -397,7 +397,7 @@ __hw_perf_event_init(struct perf_event *event)
> */
> hwc->config_base |= (unsigned long)mapping;
>
> - if (!hwc->sample_period) {
> + if (!is_sampling_event(event)) {
> /*
> * For non-sampling runs, limit the sample_period to half
> * of the counter width. That way, the new counter value
> @@ -407,6 +407,14 @@ __hw_perf_event_init(struct perf_event *event)
> hwc->sample_period = armpmu->max_period >> 1;
> hwc->last_period = hwc->sample_period;
> local64_set(&hwc->period_left, hwc->sample_period);
> + } else {
> +
> + /*
> + * If we have no PMU interrupt we cannot sample.
> + */
> + if (platform_get_irq(armpmu->plat_device, 0) < 0)
> + return -EOPNOTSUPP;
I think this should be <= 0, but apart from that this looks alright to me in
the absence of a core change.
Will
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