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Message-Id: <201401201941.07633.arnd@arndb.de>
Date: Mon, 20 Jan 2014 19:41:07 +0100
From: Arnd Bergmann <arnd@...db.de>
To: Srikanth Thokala <sthokal@...inx.com>
Cc: linux-arm-kernel@...ts.infradead.org, dan.j.williams@...el.com,
vinod.koul@...el.com, michal.simek@...inx.com,
Grant Likely <grant.likely@...aro.org>, robh+dt@...nel.org,
dmaengine@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
On Monday 20 January 2014, Srikanth Thokala wrote:
> >
> >> > * data width should be a property of the slave driver that is configured
> >> > through dma_slave_config(), unless you can have dma engines that only
> >> > support certain a width.
> >>
> >> Yes, this VDMA engine soft IP support only certain widths, which is
> >> configurable during IP synthesis.
> >
> > But what is this property used for in that case? Surely you can't
> > connect a slave device to a dmaengine if the bus width doesn't match.
> > You probably have a point here, but I don't understand it yet.
>
> There is a Data-Realignment Engine (DRE) in the IP which is only available for
> data width setting of 64-bits and less. So, we use the data-width DT parameter
> to verify this condition and we update alignment shift accordingly.
Ok, I have to admit I didn't understand all of that, but you clearly
know what you are talking about here, so I assume you are correct.
Arnd
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