linux-kernel - Re: [PATCH v2 00/21] pinctrl: mvebu: restructure and remove hardcoded addresses from Dove pinctrl

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <52EA9EFA.1030609@gmail.com>
Date:	Thu, 30 Jan 2014 19:50:34 +0100
From:	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
To:	Andrew Lunn <andrew@...n.ch>
CC:	Jason Cooper <jason@...edaemon.net>,
	Gregory Clement <gregory.clement@...e-electrons.com>,
	Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
	Russell King <linux@....linux.org.uk>,
	Linus Walleij <linus.walleij@...aro.org>,
	devicetree@...r.kernel.org, linux-doc@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 00/21] pinctrl: mvebu: restructure and remove hardcoded
 addresses from Dove pinctrl

On 01/30/2014 07:29 PM, Andrew Lunn wrote:
> On Tue, Jan 28, 2014 at 01:39:12AM +0100, Sebastian Hesselbarth wrote:
>> This patch set is one required step for Dove to hop into mach-mvebu.
>> Until now, pinctrl-dove was hardcoding some registers that do not
>> directly belong to MPP core registers. This is not compatible with
>> what we want for mach-mvebu.
>
> I think there might be something wrong here....

There _is_ something wrong. I'll have a look at it. For the record,
what SoC are you testing with? From the base address, I guess it is
Kirkwood?

Sebastian

> /debug/pinctrl/f1010000.pinctrl/pinconf-groups used to contain:
>
> Pin config settings per pin group
> Format: group (name): configs
> 0 (mpp0):current: spi(cs), available = [ gpio(io) nand(io2) ]
> 1 (mpp1):current: spi(mosi), available = [ gpo(o) nand(io3) ]
> 2 (mpp2):current: spi(sck), available = [ gpo(o) nand(io4) ]
> 3 (mpp3):current: spi(miso), available = [ gpo(o) nand(io5) ]
> 4 (mpp4):current: sata1(act), available = [ gpio(io) nand(io6) uart0(rxd) lcd(hsync) ]
> 5 (mpp5):current: sata0(act), available = [ gpo(o) nand(io7) uart0(txd) lcd(vsync) ]
> 6 (mpp6):current: sysrst(out), available = [ spi(mosi) ]
> ...
>
> It now has:
>
> Pin config settings per pin group
> Format: group (name): configs
> 0 (mpp0):current: gpio(io), available = [ nand(io2) spi(cs) ]
> 1 (mpp1):current: gpo(o), available = [ nand(io3) spi(mosi) ]
> 2 (mpp2):current: gpo(o), available = [ nand(io4) spi(sck) ]
> 3 (mpp3):current: gpo(o), available = [ nand(io5) spi(miso) ]
> 4 (mpp4):current: gpio(io), available = [ nand(io6) uart0(rxd) sata1(act) lcd(hsync) ]
> 5 (mpp5):current: gpo(o), available = [ nand(io7) uart0(txd) sata0(act) lcd(vsync) ]
> 6 (mpp6):current: UNKNOWN, available = [ sysrst(out) spi(mosi) ]
>
> The device i'm testing on does use spi and sata, so i would say the
> old contents was correct and the new is wrong.


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/