lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAC5e1FpChdyW9xzbwsyVx147hKrV0MxwkCMyKHR4ab5-Q=DyPg@mail.gmail.com>
Date:	Wed, 19 Feb 2014 10:32:44 +0800
From:	carl peng <carlpeng008@...il.com>
To:	Thomas Gleixner <tglx@...utronix.de>
Cc:	mingo@...hat.com, hpa@...or.com, x86@...nel.org,
	pingfank@...ux.vnet.ibm.com, yoshihiro.yunomae.ez@...achi.com,
	linux-kernel@...r.kernel.org
Subject: Re: Does it need to implement irq_set_type method in the ioapic_chip?

Hi Thomas,

Thanks a lot for your help!

But I still have some confusion. Could you please help to give some
suggestions to me?

1) This device is a ACPI device, the hardware engineer designed it as
falling edge interrupt trigger
mode, does it need to re-work the hardware and modify it as rising
edge trigger mode to suit the
Linux APIC driver architecture?
2) Why does APIC driver not implement the irq_set_type method?  if
implement it, will supply more
free space for the device driver developer(they can set the interrupt
trigger mode by calling request_irq).

Thank you!
Carl


On Wed, Feb 19, 2014 at 4:13 AM, Thomas Gleixner <tglx@...utronix.de> wrote:
> On Tue, 18 Feb 2014, carl peng wrote:
>
> Carl, sending the same mail twice within an hour does not speed up
> things. It's quite likely that it gets ignored.
>
>> 1. Does it need to implement irq_set_type method in the ioapic_chip
>> structure?
>
> No. The irq type is configured by the type of the interrupt or the
> BIOS.
>
> ISA  interrupts are always polarity zero edge triggered (historic)
>
> PCI  interrupts are always polarity one level triggered
>
> PCIE interrupts are either legacy PCI or with MSI[X] always edge
>      triggered
>
>> 2. if no need to implement it, how can device driver set the trigger mode
>> of APIC interrupt controller pin?
>
> Not at all.
>
> The device which is connected to one of the busses must follow the
> specification of the bus. There is no choice. Any additional
> requirements of the device to deal with external signals must be
> handled by the device itself and converted to the appropriate bus
> requirement.
>
> This all is configured by the kernel automatically through bus
> detection and BIOS tables.
>
> Thanks,
>
>         tglx
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ