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Message-ID: <20140225015923.GE7540@shlinux1.ap.freescale.net>
Date:	Tue, 25 Feb 2014 09:59:24 +0800
From:	Peter Chen <peter.chen@...escale.com>
To:	Neil Zhang <zhangwm@...vell.com>
CC:	<balbi@...com>, <gregkh@...uxfoundation.org>,
	<linux-usb@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/6] usb: gadget: mv_udc: clear corresponding interrupt
 when flush fifo

On Mon, Feb 24, 2014 at 04:03:13PM +0800, Neil Zhang wrote:
> The interruts are useless when this endpoint is going to be flushed.
> Especially in the enumeration phase, let's take get device description
> for example.
> 1. Device doesn't ACK the status package from host in time due to irq is
> disabled by some module.
> 2. Host find no ACK in time, and send another request.

Why device does not send NAK at that time?
Besides, you can try to prime status at data stage, it can also
avoid the problem usb 2.0 8.5.3.3 "Error Handling on the Last Data
Transaction" described.

> 3. Device gets the chance to handle the interrupt, the sequence is as
> following.
> 	a. Flush pending requests in ep0.
> 	b. Queue a request in ep0 according to host's request and change
> 	   the ep0 state to DATA_STATE_XMIT.
> 	c. Handle the pending interrupt for the last status package. But
> 	   actually it will check the new added request instead of the status
> 	   package and because of wront ep0 state, device will request an

%s/wront/wrong

Peter

> 	   unexpected status package from host.
> 	d. The ep0 state is going mad.
> 
> The solution is that we need clear the pending corresponding interrupt
> as well as flush
> endpoint.
> 
> Signed-off-by: Neil Zhang <zhangwm@...vell.com>
> ---
>  drivers/usb/gadget/mv_udc_core.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/usb/gadget/mv_udc_core.c b/drivers/usb/gadget/mv_udc_core.c
> index 657ac5c..d5a9bdf 100644
> --- a/drivers/usb/gadget/mv_udc_core.c
> +++ b/drivers/usb/gadget/mv_udc_core.c
> @@ -692,6 +692,8 @@ static void mv_ep_fifo_flush(struct usb_ep *_ep)
>  		}
>  		loops--;
>  	} while (readl(&udc->op_regs->epstatus) & bit_pos);
> +
> +	writel(bit_pos, &udc->op_regs->epcomplete);
>  }
>  
>  /* queues (submits) an I/O request to an endpoint */
> -- 
> 1.7.9.5
> 
> --
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> 
> 

-- 

Best Regards,
Peter Chen

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