linux-kernel - Re: [PATCH] ASoC: cs42888: Add codec driver support

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Date:	Tue, 25 Feb 2014 10:38:41 +0800
From:	Nicolin Chen <Guangyu.Chen@...escale.com>
To:	Mark Brown <broonie@...nel.org>
CC:	"Austin, Brian" <Brian.Austin@...rus.com>,
	"Handrigan, Paul" <Paul.Handrigan@...rus.com>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	"pawel.moll@....com" <pawel.moll@....com>,
	"mark.rutland@....com" <mark.rutland@....com>,
	"ijc+devicetree@...lion.org.uk" <ijc+devicetree@...lion.org.uk>,
	"galak@...eaurora.org" <galak@...eaurora.org>,
	"rob@...dley.net" <rob@...dley.net>,
	Liam Girdwood <lgirdwood@...il.com>,
	"grant.likely@...aro.org" <grant.likely@...aro.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>
Subject: Re: [PATCH] ASoC: cs42888: Add codec driver support

On Tue, Feb 25, 2014 at 09:00:27AM +0900, Mark Brown wrote:
> On Tue, Feb 25, 2014 at 12:06:49AM +0800, Nicolin Chen wrote:
> > On Mon, Feb 24, 2014 at 03:52:24PM +0000, Austin, Brian wrote:
> 
> > Wait...Regarding this clock part, I just forgot the reason I put the code:
> 
> > 385         cs42888->clk = devm_clk_get(&i2c->dev, "mclk");
> > 386         if (IS_ERR(cs42888->clk))
> > 387                 dev_warn(&i2c->dev, "failed to get the clock: %ld\n",
> > 388                                 PTR_ERR(cs42888->clk));
> 
> > was because the MCLK might be provided from SoC (DAI master) so it could
> > be totally controlled by CPU DAI driver, ESAI for example has its own
> > dividers to derive the HCKT clock (MCLK for Tx) from ahb clock in SoC
> > clock tree, in which case we might not easily pass a valid clock phandle
> > via DT. (RFC to this thought.)
> 
> We should be getting those clocks visible in the clock API rather than
> doing this.

Hmm...my words might not be so clear last time: we have to handle the dividers
of ESAI in ESAI driver because the dividers is in the ESAI's IP, not in the SoC
clock controlling unit. So it's hard to get them visible in the clock tree.

Thank you,
Nicolin



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