linux-kernel - RE: [PATCH 3/4] tile/perf: Support perf

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Message-ID: <BAB94DBB0E89D8409949BC28AC95914C5D67FFB1@USMAExch1.tad.internal.tilera.com>
Date:	Thu, 6 Mar 2014 09:57:31 +0000
From:	Tony Lu <zlu@...era.com>
To:	Peter Zijlstra <peterz@...radead.org>
CC:	Paul Mackerras <paulus@...ba.org>, Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	Chris Metcalf <cmetcalf@...era.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 3/4] tile/perf: Support perf_events on tilegx and tilepro

>-----Original Message-----
>From: Peter Zijlstra [mailto:peterz@...radead.org]
>Sent: Thursday, March 06, 2014 5:07 PM
>To: Tony Lu
>Cc: Paul Mackerras; Ingo Molnar; Arnaldo Carvalho de Melo; Chris Metcalf;
>linux-kernel@...r.kernel.org
>Subject: Re: [PATCH 3/4] tile/perf: Support perf_events on tilegx and tilepro
>
>On Thu, Mar 06, 2014 at 06:26:11AM +0000, Tony Lu wrote:
>> +static const int tile_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
>> +                                    [PERF_COUNT_HW_CACHE_OP_MAX]
>> +                                    [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
>> +[C(L1D)] = {
>> +       [C(OP_READ)] = {
>> +               [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
>> +               [C(RESULT_MISS)] = 0x21, /* RD_MISS */
>> +       },
>> +       [C(OP_WRITE)] = {
>> +               [C(RESULT_ACCESS)] = 0x22, /* WR_MISS */
>> +               [C(RESULT_MISS)] = TILE_OP_UNSUPP,
>> +       },
>
>If that's the wr_miss event as the comment says, it should probably be
>listed one down.

Yes, you are right. Thanks for pointing it out. It should be:
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+		[C(RESULT_MISS)] = 0x22, /* WR_MISS */
+	},

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