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Date:	Sun, 9 Mar 2014 10:03:39 +0100
From:	Wolfram Sang <wsa@...-dreams.de>
To:	Chew Chiau Ee <chiau.ee.chew@...el.com>
Cc:	Mika Westerberg <mika.westerberg@...ux.intel.com>,
	linux-i2c@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] i2c: designware-pci: set ideal HCNT, LCNT and SDA
 hold time value

On Fri, Mar 07, 2014 at 10:12:51PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew@...el.com>
> 
> On Intel BayTrail, there was case whereby the resulting fast mode
> bus speed becomes slower (~20% slower compared to expected speed)
> if using the HCNT/LCNT calculated in the core layer. Thus, this
> patch is added to allow pci glue layer to pass in optimal
> HCNT/LCNT/SDA hold time values to core layer since the core
> layer supports cofigurable HCNT/LCNT/SDA hold time values now.
> 
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@...el.com>

Can you make use of those instead?

        u32                     sda_falling_time;
        u32                     scl_falling_time;

This is more consistent with using sda_hold_time and lets them have a
common (and more readable) unit.


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