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Message-Id: <1395068788-19786-2-git-send-email-antoine.tenart@free-electrons.com>
Date: Mon, 17 Mar 2014 16:06:26 +0100
From: Antoine Ténart
<antoine.tenart@...e-electrons.com>
To: sebastian.hesselbarth@...il.com
Cc: Antoine Ténart
<antoine.tenart@...e-electrons.com>,
alexandre.belloni@...e-electrons.com, zmxu@...vell.com,
jszhang@...vell.com, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v3 1/3] ARM: dts: berlin2q: add the Marvell Armada 1500 pro
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).
The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local
timer, apb timers and uarts for now.
Signed-off-by: Antoine Ténart <antoine.tenart@...e-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@...e-electrons.com>
---
arch/arm/boot/dts/berlin2q.dtsi | 210 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 210 insertions(+)
create mode 100644 arch/arm/boot/dts/berlin2q.dtsi
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
new file mode 100644
index 000000000000..7a50267b1044
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2014 Antoine Ténart <antoine.tenart@...e-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
+
+/ {
+ model = "Marvell Armada 1500 pro (BG2-Q) SoC";
+ compatible = "marvell,berlin2q", "marvell,berlin";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <3>;
+ };
+ };
+
+ smclk: sysmgr-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ cpuclk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1200000000>;
+ };
+
+ sysclk: system-clock {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&cpuclk>;
+ clock-multi = <1>;
+ clock-div = <3>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xf7000000 0x1000000>;
+ interrupt-parent = <&gic>;
+
+ l2: l2-cache-controller@...000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xac0000 0x1000>;
+ cache-level = <2>;
+ };
+
+ local-timer@...600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0xad0600 0x20>;
+ clocks = <&sysclk>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gic: interrupt-controller@...000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0xad1000 0x1000>, <0xad0100 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ apb@...000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xe80000 0x10000>;
+ interrupt-parent = <&aic>;
+
+ timer0: timer@...0 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c00 0x14>;
+ interrupts = <8>;
+ clock-freq = <100000000>;
+ };
+
+ timer1: timer@...4 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c14 0x14>;
+ clock-freq = <100000000>;
+ status = "disabled";
+ };
+
+ timer2: timer@...8 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c28 0x14>;
+ clock-freq = <100000000>;
+ status = "disabled";
+ };
+
+ timer3: timer@...c {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c3c 0x14>;
+ clock-freq = <100000000>;
+ status = "disabled";
+ };
+
+ timer4: timer@...0 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c50 0x14>;
+ clock-freq = <100000000>;
+ status = "disabled";
+ };
+
+ timer5: timer@...4 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c64 0x14>;
+ clock-freq = <100000000>;
+ status = "disabled";
+ };
+
+ timer6: timer@...8 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c78 0x14>;
+ clock-freq = <100000000>;
+ status = "disabled";
+ };
+
+ timer7: timer@...c {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x2c8c 0x14>;
+ clock-freq = <100000000>;
+ status = "disabled";
+ };
+
+ aic: interrupt-controller@...0 {
+ compatible = "snps,dw-apb-ictl";
+ reg = <0x3800 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ apb@...000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xfc0000 0x10000>;
+ interrupt-parent = <&sic>;
+
+ uart0: uart@...0 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x9000 0x100>;
+ interrupt-parent = <&sic>;
+ interrupts = <8>;
+ clock-frequency = <25000000>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: uart@...0 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xa000 0x100>;
+ interrupt-parent = <&sic>;
+ interrupts = <9>;
+ clock-frequency = <25000000>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sic: interrupt-controller@...0 {
+ compatible = "snps,dw-apb-ictl";
+ reg = <0xe000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+};
--
1.8.3.2
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