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Date:	Thu, 20 Mar 2014 11:48:29 +0000
From:	Mark Brown <>
To:	Arun Shamanna Lakshmi <>
Cc:	"" <>,
	"" <>, "" <>,
	"" <>,
	"" <>,
	Songhee Baek <>,
Subject: Re: [PATCH] ASoC: Add support for multi register mux

On Wed, Mar 19, 2014 at 04:44:00PM -0700, Arun Shamanna Lakshmi wrote:

Don't top post and fix your mailer to word wrap within paragraphs, your
mail is very hard to read.

> If each bit of a 32 bit register maps to an input of a mux, then with
> the current 'soc_enum' structure we cannot have more than 64 inputs
> for the mux (because of reg and reg2 only).

What makes you say that?  We currently have devices in mainline which
have well over 32 inputs to muxes.

> For instance, the audio xbar (AXBAR) module acts as a mux selecting
> various inputs (reference: Tegra K1 manual).

I don't have access to non-public nVidia documents...

> The number of such inputs increases with future Tegra chips and so
> will be the need to control multiple registers per mux in DAPM.  We
> have 2 options to achieve that.

Like I said in my previous reply I would expect to see some users along
with the code, extending the standard helpers to support this would be a
much better idea than doing something driver custom.

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