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Date: Fri, 21 Mar 2014 13:14:13 -0500
From: delicious quinoa <delicious.quinoa@...il.com>
To: Sebastian Andrzej Siewior <bigeasy@...utronix.de>
Cc: Alan Tull <atull@...era.com>,
Linus Walleij <linus.walleij@...aro.org>,
Alexandre Courbot <gnurou@...il.com>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
Dinh Nguyen <dinguyen@...era.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH 3/3] ARM: dts: socfpga: add gpio pieces
On Thu, Mar 20, 2014 at 2:55 PM, Sebastian Andrzej Siewior
<bigeasy@...utronix.de> wrote:
> The cycloneV has three gpio controllers, each one with 29 gpios. This patch
> adds the three controller with the gpio driver which is now sitting the
> gpio tree.
>
> Cc: devicetree@...r.kernel.org
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@...utronix.de>
> ---
> arch/arm/boot/dts/socfpga.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index 537f1a5..c3a97e1 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -463,6 +463,66 @@
> status = "disabled";
> };
>
> + gpio@...08000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff708000 0x1000>;
> + clocks = <&per_base_clk>;
> + status = "disabled";
> +
> + gpio0: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <1>;
#gpio-cells = <2>;
I applied this patch, fixed the gpio-cells, tested on a cyclone5 soc
devkit, and see that it breaks the interrupts. Did you test this?
Alan
> + snps,nr-gpios = <29>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <0 164 4>;
> + };
> + };
> +
> + gpio@...09000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff709000 0x1000>;
> + clocks = <&per_base_clk>;
> + status = "disabled";
> +
> + gpio1: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <1>;
> + snps,nr-gpios = <29>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <0 165 4>;
> + };
> + };
> +
> + gpio@...0a000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff70a000 0x1000>;
> + clocks = <&per_base_clk>;
> + status = "disabled";
> +
> + gpio2: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <1>;
> + snps,nr-gpios = <29>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <0 166 4>;
> + };
> + };
> +
> L2: l2-cache@...ef000 {
> compatible = "arm,pl310-cache";
> reg = <0xfffef000 0x1000>;
> --
> 1.9.1
>
> --
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